| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.53 | 86.53 | 92.38 | 92.38 | 85.37 | 85.37 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/10.prim_esc_test.2105558214 |
| 88.86 | 2.33 | 93.33 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 10.71 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.2259636967 |
| 90.01 | 1.14 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/12.prim_esc_test.3212118711 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/4.prim_esc_test.1092232755 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1526963144 |
| /workspace/coverage/default/1.prim_esc_test.202318529 |
| /workspace/coverage/default/11.prim_esc_test.4025761181 |
| /workspace/coverage/default/13.prim_esc_test.1621281448 |
| /workspace/coverage/default/15.prim_esc_test.3306370057 |
| /workspace/coverage/default/16.prim_esc_test.1343677327 |
| /workspace/coverage/default/17.prim_esc_test.1229236858 |
| /workspace/coverage/default/18.prim_esc_test.10081104 |
| /workspace/coverage/default/19.prim_esc_test.3166783650 |
| /workspace/coverage/default/2.prim_esc_test.3538486246 |
| /workspace/coverage/default/3.prim_esc_test.90940671 |
| /workspace/coverage/default/5.prim_esc_test.1945258340 |
| /workspace/coverage/default/6.prim_esc_test.2417161814 |
| /workspace/coverage/default/7.prim_esc_test.4225659438 |
| /workspace/coverage/default/8.prim_esc_test.3920171217 |
| /workspace/coverage/default/9.prim_esc_test.3376904416 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/11.prim_esc_test.4025761181 | Jul 06 04:19:36 PM PDT 24 | Jul 06 04:19:38 PM PDT 24 | 4812065 ps | ||
| T2 | /workspace/coverage/default/0.prim_esc_test.1526963144 | Jul 06 04:18:39 PM PDT 24 | Jul 06 04:18:40 PM PDT 24 | 4947786 ps | ||
| T3 | /workspace/coverage/default/15.prim_esc_test.3306370057 | Jul 06 04:19:26 PM PDT 24 | Jul 06 04:19:26 PM PDT 24 | 4975405 ps | ||
| T4 | /workspace/coverage/default/10.prim_esc_test.2105558214 | Jul 06 04:19:36 PM PDT 24 | Jul 06 04:19:38 PM PDT 24 | 4795515 ps | ||
| T8 | /workspace/coverage/default/3.prim_esc_test.90940671 | Jul 06 04:19:36 PM PDT 24 | Jul 06 04:19:37 PM PDT 24 | 4904546 ps | ||
| T11 | /workspace/coverage/default/2.prim_esc_test.3538486246 | Jul 06 04:18:39 PM PDT 24 | Jul 06 04:18:40 PM PDT 24 | 4244784 ps | ||
| T10 | /workspace/coverage/default/19.prim_esc_test.3166783650 | Jul 06 04:20:21 PM PDT 24 | Jul 06 04:20:22 PM PDT 24 | 5348902 ps | ||
| T16 | /workspace/coverage/default/8.prim_esc_test.3920171217 | Jul 06 04:19:31 PM PDT 24 | Jul 06 04:19:31 PM PDT 24 | 4404539 ps | ||
| T5 | /workspace/coverage/default/4.prim_esc_test.1092232755 | Jul 06 04:19:51 PM PDT 24 | Jul 06 04:19:51 PM PDT 24 | 5267176 ps | ||
| T12 | /workspace/coverage/default/1.prim_esc_test.202318529 | Jul 06 04:19:36 PM PDT 24 | Jul 06 04:19:38 PM PDT 24 | 4440095 ps | ||
| T13 | /workspace/coverage/default/13.prim_esc_test.1621281448 | Jul 06 04:19:05 PM PDT 24 | Jul 06 04:19:05 PM PDT 24 | 4579510 ps | ||
| T14 | /workspace/coverage/default/14.prim_esc_test.2259636967 | Jul 06 04:19:04 PM PDT 24 | Jul 06 04:19:05 PM PDT 24 | 5398562 ps | ||
| T6 | /workspace/coverage/default/12.prim_esc_test.3212118711 | Jul 06 04:19:05 PM PDT 24 | Jul 06 04:19:06 PM PDT 24 | 4479770 ps | ||
| T7 | /workspace/coverage/default/7.prim_esc_test.4225659438 | Jul 06 04:18:53 PM PDT 24 | Jul 06 04:18:53 PM PDT 24 | 4433830 ps | ||
| T17 | /workspace/coverage/default/18.prim_esc_test.10081104 | Jul 06 04:20:20 PM PDT 24 | Jul 06 04:20:21 PM PDT 24 | 4945129 ps | ||
| T15 | /workspace/coverage/default/9.prim_esc_test.3376904416 | Jul 06 04:23:42 PM PDT 24 | Jul 06 04:23:43 PM PDT 24 | 4713569 ps | ||
| T18 | /workspace/coverage/default/16.prim_esc_test.1343677327 | Jul 06 04:18:39 PM PDT 24 | Jul 06 04:18:40 PM PDT 24 | 4966877 ps | ||
| T9 | /workspace/coverage/default/5.prim_esc_test.1945258340 | Jul 06 04:19:36 PM PDT 24 | Jul 06 04:19:38 PM PDT 24 | 4650044 ps | ||
| T19 | /workspace/coverage/default/17.prim_esc_test.1229236858 | Jul 06 04:23:42 PM PDT 24 | Jul 06 04:23:43 PM PDT 24 | 5063270 ps | ||
| T20 | /workspace/coverage/default/6.prim_esc_test.2417161814 | Jul 06 04:18:58 PM PDT 24 | Jul 06 04:18:58 PM PDT 24 | 4771947 ps |
| Test location | /workspace/coverage/default/10.prim_esc_test.2105558214 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4795515 ps |
| CPU time | 0.36 seconds |
| Started | Jul 06 04:19:36 PM PDT 24 |
| Finished | Jul 06 04:19:38 PM PDT 24 |
| Peak memory | 146272 kb |
| Host | smart-d82de99d-2955-4b88-9e25-b6df5354c4be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105558214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2105558214 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2259636967 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5398562 ps |
| CPU time | 0.42 seconds |
| Started | Jul 06 04:19:04 PM PDT 24 |
| Finished | Jul 06 04:19:05 PM PDT 24 |
| Peak memory | 146352 kb |
| Host | smart-d63f9f74-6618-45e1-a00c-979c1949127f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259636967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2259636967 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3212118711 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4479770 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:19:05 PM PDT 24 |
| Finished | Jul 06 04:19:06 PM PDT 24 |
| Peak memory | 146352 kb |
| Host | smart-8ba390d6-93fe-4d9f-8db7-542c73c583f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3212118711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3212118711 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1092232755 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5267176 ps |
| CPU time | 0.39 seconds |
| Started | Jul 06 04:19:51 PM PDT 24 |
| Finished | Jul 06 04:19:51 PM PDT 24 |
| Peak memory | 145756 kb |
| Host | smart-ec292931-a437-4440-9029-e6fcf90bc0ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1092232755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1092232755 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1526963144 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4947786 ps |
| CPU time | 0.43 seconds |
| Started | Jul 06 04:18:39 PM PDT 24 |
| Finished | Jul 06 04:18:40 PM PDT 24 |
| Peak memory | 144780 kb |
| Host | smart-396c10c6-879a-4397-b6a4-267f2fe57c51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1526963144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1526963144 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.202318529 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4440095 ps |
| CPU time | 0.37 seconds |
| Started | Jul 06 04:19:36 PM PDT 24 |
| Finished | Jul 06 04:19:38 PM PDT 24 |
| Peak memory | 146100 kb |
| Host | smart-6be02d25-ece7-4ab2-8be5-3e98fbdb98dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=202318529 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.202318529 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.4025761181 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4812065 ps |
| CPU time | 0.43 seconds |
| Started | Jul 06 04:19:36 PM PDT 24 |
| Finished | Jul 06 04:19:38 PM PDT 24 |
| Peak memory | 144388 kb |
| Host | smart-05473439-73e7-47d7-bf55-ab189b480174 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4025761181 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.4025761181 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1621281448 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4579510 ps |
| CPU time | 0.41 seconds |
| Started | Jul 06 04:19:05 PM PDT 24 |
| Finished | Jul 06 04:19:05 PM PDT 24 |
| Peak memory | 146352 kb |
| Host | smart-ff423a15-b8b0-4a9c-8b69-e1c9d2f747f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1621281448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1621281448 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3306370057 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4975405 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:19:26 PM PDT 24 |
| Finished | Jul 06 04:19:26 PM PDT 24 |
| Peak memory | 145996 kb |
| Host | smart-3f91bc99-8a63-4c7d-acd7-e28ea4cc87a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3306370057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3306370057 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1343677327 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4966877 ps |
| CPU time | 0.44 seconds |
| Started | Jul 06 04:18:39 PM PDT 24 |
| Finished | Jul 06 04:18:40 PM PDT 24 |
| Peak memory | 145212 kb |
| Host | smart-86963bf8-a558-4604-9163-0078b24da9cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1343677327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1343677327 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1229236858 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5063270 ps |
| CPU time | 0.41 seconds |
| Started | Jul 06 04:23:42 PM PDT 24 |
| Finished | Jul 06 04:23:43 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-8f2c8941-9a0d-48de-8432-892668ed2c97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229236858 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1229236858 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.10081104 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4945129 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:20:20 PM PDT 24 |
| Finished | Jul 06 04:20:21 PM PDT 24 |
| Peak memory | 145960 kb |
| Host | smart-59dbd7fb-5ef1-44de-b24e-b435efa7e92a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10081104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.10081104 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3166783650 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5348902 ps |
| CPU time | 0.38 seconds |
| Started | Jul 06 04:20:21 PM PDT 24 |
| Finished | Jul 06 04:20:22 PM PDT 24 |
| Peak memory | 146028 kb |
| Host | smart-87d336ab-ea56-442f-9f0f-de74715acebe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3166783650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3166783650 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3538486246 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4244784 ps |
| CPU time | 0.41 seconds |
| Started | Jul 06 04:18:39 PM PDT 24 |
| Finished | Jul 06 04:18:40 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-c873b170-803a-4b67-a360-3a2448fd0a66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3538486246 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3538486246 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.90940671 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4904546 ps |
| CPU time | 0.37 seconds |
| Started | Jul 06 04:19:36 PM PDT 24 |
| Finished | Jul 06 04:19:37 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-1b81392a-6812-4286-8ee4-f6ec53279166 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=90940671 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.90940671 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1945258340 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4650044 ps |
| CPU time | 0.5 seconds |
| Started | Jul 06 04:19:36 PM PDT 24 |
| Finished | Jul 06 04:19:38 PM PDT 24 |
| Peak memory | 144064 kb |
| Host | smart-d2b6f185-a6ee-4ad3-a1f5-d6caddd8f022 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945258340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1945258340 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2417161814 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4771947 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:18:58 PM PDT 24 |
| Finished | Jul 06 04:18:58 PM PDT 24 |
| Peak memory | 146020 kb |
| Host | smart-c7b339cf-3f89-43f4-b2e7-108c5a82cc73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2417161814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2417161814 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.4225659438 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4433830 ps |
| CPU time | 0.4 seconds |
| Started | Jul 06 04:18:53 PM PDT 24 |
| Finished | Jul 06 04:18:53 PM PDT 24 |
| Peak memory | 146064 kb |
| Host | smart-f976988a-2559-4e0b-8cb4-39d313129d9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4225659438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4225659438 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3920171217 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4404539 ps |
| CPU time | 0.37 seconds |
| Started | Jul 06 04:19:31 PM PDT 24 |
| Finished | Jul 06 04:19:31 PM PDT 24 |
| Peak memory | 146044 kb |
| Host | smart-7ce2b97e-5293-4511-ae20-762a2708f7bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3920171217 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3920171217 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3376904416 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4713569 ps |
| CPU time | 0.44 seconds |
| Started | Jul 06 04:23:42 PM PDT 24 |
| Finished | Jul 06 04:23:43 PM PDT 24 |
| Peak memory | 145236 kb |
| Host | smart-54c535b9-081c-4bec-904d-1fc8afe04a66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376904416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3376904416 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |