| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.31 | 85.31 | 92.38 | 92.38 | 78.05 | 78.05 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/13.prim_esc_test.3899173600 |
| 88.27 | 2.96 | 93.33 | 0.95 | 85.37 | 7.32 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.482788436 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/19.prim_esc_test.2811317248 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.4171991421 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.3706159875 |
| /workspace/coverage/default/1.prim_esc_test.784420995 |
| /workspace/coverage/default/10.prim_esc_test.3839756525 |
| /workspace/coverage/default/11.prim_esc_test.245171603 |
| /workspace/coverage/default/12.prim_esc_test.4196015680 |
| /workspace/coverage/default/16.prim_esc_test.2791678785 |
| /workspace/coverage/default/17.prim_esc_test.373984098 |
| /workspace/coverage/default/18.prim_esc_test.2575137762 |
| /workspace/coverage/default/2.prim_esc_test.3688354886 |
| /workspace/coverage/default/3.prim_esc_test.2427921230 |
| /workspace/coverage/default/4.prim_esc_test.1510291034 |
| /workspace/coverage/default/5.prim_esc_test.1837069023 |
| /workspace/coverage/default/6.prim_esc_test.1633253401 |
| /workspace/coverage/default/7.prim_esc_test.1170900852 |
| /workspace/coverage/default/8.prim_esc_test.2135188888 |
| /workspace/coverage/default/9.prim_esc_test.958088756 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/13.prim_esc_test.3899173600 | Jul 07 04:45:53 PM PDT 24 | Jul 07 04:45:54 PM PDT 24 | 4470032 ps | ||
| T2 | /workspace/coverage/default/3.prim_esc_test.2427921230 | Jul 07 04:46:07 PM PDT 24 | Jul 07 04:46:08 PM PDT 24 | 5093048 ps | ||
| T3 | /workspace/coverage/default/16.prim_esc_test.2791678785 | Jul 07 04:45:52 PM PDT 24 | Jul 07 04:45:53 PM PDT 24 | 4920743 ps | ||
| T7 | /workspace/coverage/default/11.prim_esc_test.245171603 | Jul 07 04:46:12 PM PDT 24 | Jul 07 04:46:13 PM PDT 24 | 4641232 ps | ||
| T10 | /workspace/coverage/default/2.prim_esc_test.3688354886 | Jul 07 04:45:54 PM PDT 24 | Jul 07 04:45:55 PM PDT 24 | 4873323 ps | ||
| T4 | /workspace/coverage/default/19.prim_esc_test.2811317248 | Jul 07 04:45:58 PM PDT 24 | Jul 07 04:45:59 PM PDT 24 | 4722416 ps | ||
| T14 | /workspace/coverage/default/10.prim_esc_test.3839756525 | Jul 07 04:45:54 PM PDT 24 | Jul 07 04:45:54 PM PDT 24 | 5164346 ps | ||
| T15 | /workspace/coverage/default/5.prim_esc_test.1837069023 | Jul 07 04:46:11 PM PDT 24 | Jul 07 04:46:16 PM PDT 24 | 5052029 ps | ||
| T16 | /workspace/coverage/default/18.prim_esc_test.2575137762 | Jul 07 04:46:06 PM PDT 24 | Jul 07 04:46:07 PM PDT 24 | 5330273 ps | ||
| T6 | /workspace/coverage/default/9.prim_esc_test.958088756 | Jul 07 04:46:03 PM PDT 24 | Jul 07 04:46:04 PM PDT 24 | 4933357 ps | ||
| T13 | /workspace/coverage/default/1.prim_esc_test.784420995 | Jul 07 04:45:53 PM PDT 24 | Jul 07 04:45:53 PM PDT 24 | 4592263 ps | ||
| T5 | /workspace/coverage/default/8.prim_esc_test.2135188888 | Jul 07 04:46:04 PM PDT 24 | Jul 07 04:46:05 PM PDT 24 | 4845627 ps | ||
| T12 | /workspace/coverage/default/14.prim_esc_test.482788436 | Jul 07 04:45:52 PM PDT 24 | Jul 07 04:45:52 PM PDT 24 | 4810538 ps | ||
| T8 | /workspace/coverage/default/6.prim_esc_test.1633253401 | Jul 07 04:45:54 PM PDT 24 | Jul 07 04:45:55 PM PDT 24 | 4485145 ps | ||
| T9 | /workspace/coverage/default/15.prim_esc_test.4171991421 | Jul 07 04:46:03 PM PDT 24 | Jul 07 04:46:03 PM PDT 24 | 4493815 ps | ||
| T17 | /workspace/coverage/default/4.prim_esc_test.1510291034 | Jul 07 04:45:57 PM PDT 24 | Jul 07 04:45:58 PM PDT 24 | 4724208 ps | ||
| T11 | /workspace/coverage/default/17.prim_esc_test.373984098 | Jul 07 04:45:52 PM PDT 24 | Jul 07 04:45:53 PM PDT 24 | 4748975 ps | ||
| T18 | /workspace/coverage/default/7.prim_esc_test.1170900852 | Jul 07 04:46:08 PM PDT 24 | Jul 07 04:46:08 PM PDT 24 | 4275589 ps | ||
| T19 | /workspace/coverage/default/0.prim_esc_test.3706159875 | Jul 07 04:45:50 PM PDT 24 | Jul 07 04:45:50 PM PDT 24 | 4831337 ps | ||
| T20 | /workspace/coverage/default/12.prim_esc_test.4196015680 | Jul 07 04:46:05 PM PDT 24 | Jul 07 04:46:06 PM PDT 24 | 4620515 ps |
| Test location | /workspace/coverage/default/13.prim_esc_test.3899173600 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4470032 ps |
| CPU time | 0.38 seconds |
| Started | Jul 07 04:45:53 PM PDT 24 |
| Finished | Jul 07 04:45:54 PM PDT 24 |
| Peak memory | 146016 kb |
| Host | smart-ec9d572c-a6bb-47ad-b020-5862b1afc543 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899173600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3899173600 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.482788436 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4810538 ps |
| CPU time | 0.4 seconds |
| Started | Jul 07 04:45:52 PM PDT 24 |
| Finished | Jul 07 04:45:52 PM PDT 24 |
| Peak memory | 146020 kb |
| Host | smart-bca0a4f8-7c7a-4e43-8886-1a54c3e7108e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482788436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.482788436 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2811317248 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4722416 ps |
| CPU time | 0.38 seconds |
| Started | Jul 07 04:45:58 PM PDT 24 |
| Finished | Jul 07 04:45:59 PM PDT 24 |
| Peak memory | 145948 kb |
| Host | smart-234e8626-d365-4cd2-b9ac-42c7c5a3a7f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2811317248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2811317248 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.4171991421 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4493815 ps |
| CPU time | 0.36 seconds |
| Started | Jul 07 04:46:03 PM PDT 24 |
| Finished | Jul 07 04:46:03 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-920e0956-54be-4953-8150-70cf113421f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4171991421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.4171991421 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3706159875 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4831337 ps |
| CPU time | 0.38 seconds |
| Started | Jul 07 04:45:50 PM PDT 24 |
| Finished | Jul 07 04:45:50 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-b3b63dcb-1bd0-4c95-9db3-f6aab53597f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3706159875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3706159875 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.784420995 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4592263 ps |
| CPU time | 0.37 seconds |
| Started | Jul 07 04:45:53 PM PDT 24 |
| Finished | Jul 07 04:45:53 PM PDT 24 |
| Peak memory | 145996 kb |
| Host | smart-3a9b1da3-f884-44aa-a5d4-9dbae0e2295f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=784420995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.784420995 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3839756525 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5164346 ps |
| CPU time | 0.37 seconds |
| Started | Jul 07 04:45:54 PM PDT 24 |
| Finished | Jul 07 04:45:54 PM PDT 24 |
| Peak memory | 145980 kb |
| Host | smart-3bf919ed-8538-4d3d-a6ee-6ce554b9d0e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839756525 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3839756525 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.245171603 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4641232 ps |
| CPU time | 0.38 seconds |
| Started | Jul 07 04:46:12 PM PDT 24 |
| Finished | Jul 07 04:46:13 PM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-d42ae78b-a582-4fbe-b399-5ae233ca4c4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=245171603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.245171603 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.4196015680 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4620515 ps |
| CPU time | 0.39 seconds |
| Started | Jul 07 04:46:05 PM PDT 24 |
| Finished | Jul 07 04:46:06 PM PDT 24 |
| Peak memory | 145988 kb |
| Host | smart-d7ce84a6-2400-48c3-b2f7-6c10453b8d18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4196015680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.4196015680 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2791678785 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4920743 ps |
| CPU time | 0.37 seconds |
| Started | Jul 07 04:45:52 PM PDT 24 |
| Finished | Jul 07 04:45:53 PM PDT 24 |
| Peak memory | 146008 kb |
| Host | smart-883e4426-0c80-4014-9a98-36e2085066ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2791678785 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2791678785 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.373984098 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4748975 ps |
| CPU time | 0.37 seconds |
| Started | Jul 07 04:45:52 PM PDT 24 |
| Finished | Jul 07 04:45:53 PM PDT 24 |
| Peak memory | 145992 kb |
| Host | smart-051dec94-f835-454f-8d73-33042a098b40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=373984098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.373984098 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2575137762 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5330273 ps |
| CPU time | 0.38 seconds |
| Started | Jul 07 04:46:06 PM PDT 24 |
| Finished | Jul 07 04:46:07 PM PDT 24 |
| Peak memory | 146032 kb |
| Host | smart-2b48fd70-f9cc-4364-9a73-629a9f269e75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575137762 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2575137762 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3688354886 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4873323 ps |
| CPU time | 0.38 seconds |
| Started | Jul 07 04:45:54 PM PDT 24 |
| Finished | Jul 07 04:45:55 PM PDT 24 |
| Peak memory | 145668 kb |
| Host | smart-a4edcaf8-a5ff-4340-8783-056ab36b1c3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3688354886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3688354886 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2427921230 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5093048 ps |
| CPU time | 0.4 seconds |
| Started | Jul 07 04:46:07 PM PDT 24 |
| Finished | Jul 07 04:46:08 PM PDT 24 |
| Peak memory | 145960 kb |
| Host | smart-4149e2cb-f4ec-462d-bcd5-4984b220a9d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2427921230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2427921230 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1510291034 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4724208 ps |
| CPU time | 0.37 seconds |
| Started | Jul 07 04:45:57 PM PDT 24 |
| Finished | Jul 07 04:45:58 PM PDT 24 |
| Peak memory | 145940 kb |
| Host | smart-cb264856-009c-400b-ae12-9cab5a80769d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510291034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1510291034 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1837069023 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5052029 ps |
| CPU time | 0.42 seconds |
| Started | Jul 07 04:46:11 PM PDT 24 |
| Finished | Jul 07 04:46:16 PM PDT 24 |
| Peak memory | 145904 kb |
| Host | smart-ed86281d-b354-415c-9d7d-6a7c40352696 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1837069023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1837069023 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1633253401 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4485145 ps |
| CPU time | 0.37 seconds |
| Started | Jul 07 04:45:54 PM PDT 24 |
| Finished | Jul 07 04:45:55 PM PDT 24 |
| Peak memory | 145756 kb |
| Host | smart-7f4a0e8d-e67c-47ca-acee-795379b0eded |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633253401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1633253401 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1170900852 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4275589 ps |
| CPU time | 0.39 seconds |
| Started | Jul 07 04:46:08 PM PDT 24 |
| Finished | Jul 07 04:46:08 PM PDT 24 |
| Peak memory | 145940 kb |
| Host | smart-2e3ce2a0-938d-416d-8b60-6013f2fcefd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170900852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1170900852 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2135188888 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4845627 ps |
| CPU time | 0.37 seconds |
| Started | Jul 07 04:46:04 PM PDT 24 |
| Finished | Jul 07 04:46:05 PM PDT 24 |
| Peak memory | 145920 kb |
| Host | smart-2e9a2a31-778f-43c3-ad9f-47ebf1804c78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2135188888 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2135188888 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.958088756 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4933357 ps |
| CPU time | 0.37 seconds |
| Started | Jul 07 04:46:03 PM PDT 24 |
| Finished | Jul 07 04:46:04 PM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-6c09ac7a-6770-4dbb-834b-81817b7e92a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=958088756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.958088756 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |