Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.12 85.12 92.38 92.38 80.49 80.49 100.00 100.00 75.00 75.00 81.40 81.40 81.48 81.48 /workspace/coverage/default/18.prim_esc_test.3500321144
88.27 3.15 93.33 0.95 85.37 4.88 100.00 0.00 85.71 10.71 83.72 2.33 81.48 0.00 /workspace/coverage/default/0.prim_esc_test.3232521674
90.01 1.74 94.29 0.95 85.37 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/11.prim_esc_test.4210551046
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/10.prim_esc_test.413111502

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.4004584385
/workspace/coverage/default/12.prim_esc_test.3188623700
/workspace/coverage/default/13.prim_esc_test.2545340728
/workspace/coverage/default/14.prim_esc_test.4000943164
/workspace/coverage/default/15.prim_esc_test.518494308
/workspace/coverage/default/16.prim_esc_test.480265342
/workspace/coverage/default/17.prim_esc_test.3295486034
/workspace/coverage/default/19.prim_esc_test.328630345
/workspace/coverage/default/2.prim_esc_test.1251423704
/workspace/coverage/default/3.prim_esc_test.3525826704
/workspace/coverage/default/4.prim_esc_test.1177139522
/workspace/coverage/default/5.prim_esc_test.3922519238
/workspace/coverage/default/6.prim_esc_test.2655301755
/workspace/coverage/default/7.prim_esc_test.3259104007
/workspace/coverage/default/8.prim_esc_test.2227884893
/workspace/coverage/default/9.prim_esc_test.3298588816



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.prim_esc_test.3232521674 Jul 09 04:20:53 PM PDT 24 Jul 09 04:20:54 PM PDT 24 4628564 ps
T2 /workspace/coverage/default/10.prim_esc_test.413111502 Jul 09 04:20:53 PM PDT 24 Jul 09 04:20:54 PM PDT 24 5438514 ps
T3 /workspace/coverage/default/8.prim_esc_test.2227884893 Jul 09 04:20:57 PM PDT 24 Jul 09 04:20:58 PM PDT 24 4225790 ps
T6 /workspace/coverage/default/15.prim_esc_test.518494308 Jul 09 04:20:55 PM PDT 24 Jul 09 04:20:57 PM PDT 24 4878856 ps
T9 /workspace/coverage/default/14.prim_esc_test.4000943164 Jul 09 04:20:52 PM PDT 24 Jul 09 04:20:53 PM PDT 24 4503527 ps
T4 /workspace/coverage/default/6.prim_esc_test.2655301755 Jul 09 04:20:56 PM PDT 24 Jul 09 04:20:57 PM PDT 24 5283854 ps
T13 /workspace/coverage/default/7.prim_esc_test.3259104007 Jul 09 04:20:53 PM PDT 24 Jul 09 04:20:54 PM PDT 24 5415866 ps
T14 /workspace/coverage/default/9.prim_esc_test.3298588816 Jul 09 04:20:53 PM PDT 24 Jul 09 04:20:54 PM PDT 24 4905698 ps
T15 /workspace/coverage/default/13.prim_esc_test.2545340728 Jul 09 04:20:56 PM PDT 24 Jul 09 04:20:58 PM PDT 24 5127246 ps
T5 /workspace/coverage/default/18.prim_esc_test.3500321144 Jul 09 04:20:56 PM PDT 24 Jul 09 04:20:57 PM PDT 24 4460802 ps
T12 /workspace/coverage/default/2.prim_esc_test.1251423704 Jul 09 04:20:53 PM PDT 24 Jul 09 04:20:54 PM PDT 24 5550744 ps
T16 /workspace/coverage/default/3.prim_esc_test.3525826704 Jul 09 04:20:55 PM PDT 24 Jul 09 04:20:56 PM PDT 24 4628337 ps
T17 /workspace/coverage/default/16.prim_esc_test.480265342 Jul 09 04:20:53 PM PDT 24 Jul 09 04:20:54 PM PDT 24 4572791 ps
T8 /workspace/coverage/default/5.prim_esc_test.3922519238 Jul 09 04:20:53 PM PDT 24 Jul 09 04:20:54 PM PDT 24 4884019 ps
T10 /workspace/coverage/default/1.prim_esc_test.4004584385 Jul 09 04:20:56 PM PDT 24 Jul 09 04:20:57 PM PDT 24 4749597 ps
T18 /workspace/coverage/default/17.prim_esc_test.3295486034 Jul 09 04:20:53 PM PDT 24 Jul 09 04:20:54 PM PDT 24 4742827 ps
T7 /workspace/coverage/default/12.prim_esc_test.3188623700 Jul 09 04:20:56 PM PDT 24 Jul 09 04:20:57 PM PDT 24 4773124 ps
T19 /workspace/coverage/default/19.prim_esc_test.328630345 Jul 09 04:20:57 PM PDT 24 Jul 09 04:20:58 PM PDT 24 4975423 ps
T20 /workspace/coverage/default/4.prim_esc_test.1177139522 Jul 09 04:20:53 PM PDT 24 Jul 09 04:20:54 PM PDT 24 5213609 ps
T11 /workspace/coverage/default/11.prim_esc_test.4210551046 Jul 09 04:20:56 PM PDT 24 Jul 09 04:20:57 PM PDT 24 4822591 ps

Test location /workspace/coverage/default/18.prim_esc_test.3500321144
Short name T5
Test name
Test status
Simulation time 4460802 ps
CPU time 0.36 seconds
Started Jul 09 04:20:56 PM PDT 24
Finished Jul 09 04:20:57 PM PDT 24
Peak memory 145512 kb
Host smart-d557b5bd-8840-4f77-9c49-7888e2760925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500321144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3500321144
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.3232521674
Short name T1
Test name
Test status
Simulation time 4628564 ps
CPU time 0.38 seconds
Started Jul 09 04:20:53 PM PDT 24
Finished Jul 09 04:20:54 PM PDT 24
Peak memory 145160 kb
Host smart-adc00f30-4294-43b5-801c-fe159bba407a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232521674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3232521674
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.4210551046
Short name T11
Test name
Test status
Simulation time 4822591 ps
CPU time 0.39 seconds
Started Jul 09 04:20:56 PM PDT 24
Finished Jul 09 04:20:57 PM PDT 24
Peak memory 146488 kb
Host smart-e80f4915-4bf4-4627-a14e-16da991cea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210551046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.4210551046
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.413111502
Short name T2
Test name
Test status
Simulation time 5438514 ps
CPU time 0.38 seconds
Started Jul 09 04:20:53 PM PDT 24
Finished Jul 09 04:20:54 PM PDT 24
Peak memory 146360 kb
Host smart-957de977-6afc-4150-8221-2f3dbc161fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413111502 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.413111502
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.4004584385
Short name T10
Test name
Test status
Simulation time 4749597 ps
CPU time 0.37 seconds
Started Jul 09 04:20:56 PM PDT 24
Finished Jul 09 04:20:57 PM PDT 24
Peak memory 145568 kb
Host smart-39db5d40-2ecf-42e0-8ab3-26be50fb3b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004584385 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.4004584385
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.3188623700
Short name T7
Test name
Test status
Simulation time 4773124 ps
CPU time 0.38 seconds
Started Jul 09 04:20:56 PM PDT 24
Finished Jul 09 04:20:57 PM PDT 24
Peak memory 146336 kb
Host smart-a173b369-b8bb-4cc4-a3d5-e95005e02727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188623700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3188623700
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.2545340728
Short name T15
Test name
Test status
Simulation time 5127246 ps
CPU time 0.37 seconds
Started Jul 09 04:20:56 PM PDT 24
Finished Jul 09 04:20:58 PM PDT 24
Peak memory 145612 kb
Host smart-66fbeef5-7324-44e2-b367-785eddcc3904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545340728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2545340728
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.4000943164
Short name T9
Test name
Test status
Simulation time 4503527 ps
CPU time 0.37 seconds
Started Jul 09 04:20:52 PM PDT 24
Finished Jul 09 04:20:53 PM PDT 24
Peak memory 146356 kb
Host smart-67937f53-7dc0-4630-84c5-255966f3c6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000943164 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.4000943164
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.518494308
Short name T6
Test name
Test status
Simulation time 4878856 ps
CPU time 0.41 seconds
Started Jul 09 04:20:55 PM PDT 24
Finished Jul 09 04:20:57 PM PDT 24
Peak memory 146040 kb
Host smart-fe108c86-b4c3-4224-8f0c-e7dcd2022134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518494308 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.518494308
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.480265342
Short name T17
Test name
Test status
Simulation time 4572791 ps
CPU time 0.4 seconds
Started Jul 09 04:20:53 PM PDT 24
Finished Jul 09 04:20:54 PM PDT 24
Peak memory 144912 kb
Host smart-0c65d6ad-15d4-4dd7-97a7-5a4c6829321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480265342 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.480265342
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.3295486034
Short name T18
Test name
Test status
Simulation time 4742827 ps
CPU time 0.39 seconds
Started Jul 09 04:20:53 PM PDT 24
Finished Jul 09 04:20:54 PM PDT 24
Peak memory 146356 kb
Host smart-d2b11026-00ef-442f-b774-6e404baecf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295486034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3295486034
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.328630345
Short name T19
Test name
Test status
Simulation time 4975423 ps
CPU time 0.37 seconds
Started Jul 09 04:20:57 PM PDT 24
Finished Jul 09 04:20:58 PM PDT 24
Peak memory 146360 kb
Host smart-7e9c76fc-527e-4cce-9ca2-19101e88abc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328630345 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.328630345
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.1251423704
Short name T12
Test name
Test status
Simulation time 5550744 ps
CPU time 0.4 seconds
Started Jul 09 04:20:53 PM PDT 24
Finished Jul 09 04:20:54 PM PDT 24
Peak memory 146356 kb
Host smart-12a60573-7e53-4c49-a297-9f04f0a8c48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251423704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1251423704
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.3525826704
Short name T16
Test name
Test status
Simulation time 4628337 ps
CPU time 0.38 seconds
Started Jul 09 04:20:55 PM PDT 24
Finished Jul 09 04:20:56 PM PDT 24
Peak memory 146356 kb
Host smart-0f112c42-d5dd-4f50-8154-a06e6b329f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525826704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3525826704
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.1177139522
Short name T20
Test name
Test status
Simulation time 5213609 ps
CPU time 0.37 seconds
Started Jul 09 04:20:53 PM PDT 24
Finished Jul 09 04:20:54 PM PDT 24
Peak memory 145560 kb
Host smart-2ce0f080-d024-4c94-a6bf-e5af0be81cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177139522 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1177139522
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.3922519238
Short name T8
Test name
Test status
Simulation time 4884019 ps
CPU time 0.37 seconds
Started Jul 09 04:20:53 PM PDT 24
Finished Jul 09 04:20:54 PM PDT 24
Peak memory 146632 kb
Host smart-f9c2e4f1-dd52-4ff3-843c-8f5619ee91c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922519238 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3922519238
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.2655301755
Short name T4
Test name
Test status
Simulation time 5283854 ps
CPU time 0.41 seconds
Started Jul 09 04:20:56 PM PDT 24
Finished Jul 09 04:20:57 PM PDT 24
Peak memory 145564 kb
Host smart-588de490-bc6b-481a-bedd-e85ae5482288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655301755 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2655301755
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.3259104007
Short name T13
Test name
Test status
Simulation time 5415866 ps
CPU time 0.41 seconds
Started Jul 09 04:20:53 PM PDT 24
Finished Jul 09 04:20:54 PM PDT 24
Peak memory 145236 kb
Host smart-37a9c115-f2e6-481f-9c8c-f2c7143812fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259104007 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3259104007
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.2227884893
Short name T3
Test name
Test status
Simulation time 4225790 ps
CPU time 0.4 seconds
Started Jul 09 04:20:57 PM PDT 24
Finished Jul 09 04:20:58 PM PDT 24
Peak memory 145624 kb
Host smart-cc484ada-67d7-4c14-adb5-ea1764969fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227884893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2227884893
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.3298588816
Short name T14
Test name
Test status
Simulation time 4905698 ps
CPU time 0.37 seconds
Started Jul 09 04:20:53 PM PDT 24
Finished Jul 09 04:20:54 PM PDT 24
Peak memory 145576 kb
Host smart-57a7f907-8a07-4153-b39e-e960a70e6c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298588816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3298588816
Directory /workspace/9.prim_esc_test/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%