| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.53 | 85.53 | 92.38 | 92.38 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/18.prim_esc_test.767422235 |
| 87.67 | 2.14 | 93.33 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 82.14 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/17.prim_esc_test.1897770955 |
| 89.41 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/2.prim_esc_test.391926096 |
| 90.55 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.2151038507 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.887930752 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.3352409336 |
| /workspace/coverage/default/1.prim_esc_test.1814977475 |
| /workspace/coverage/default/10.prim_esc_test.818633312 |
| /workspace/coverage/default/11.prim_esc_test.2922051947 |
| /workspace/coverage/default/12.prim_esc_test.1817138056 |
| /workspace/coverage/default/15.prim_esc_test.268597783 |
| /workspace/coverage/default/16.prim_esc_test.762681255 |
| /workspace/coverage/default/19.prim_esc_test.2476361531 |
| /workspace/coverage/default/3.prim_esc_test.1666545705 |
| /workspace/coverage/default/4.prim_esc_test.712916145 |
| /workspace/coverage/default/5.prim_esc_test.3962496406 |
| /workspace/coverage/default/6.prim_esc_test.2964762350 |
| /workspace/coverage/default/7.prim_esc_test.1807612918 |
| /workspace/coverage/default/8.prim_esc_test.296241436 |
| /workspace/coverage/default/9.prim_esc_test.372649200 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/10.prim_esc_test.818633312 | Jul 10 04:19:38 PM PDT 24 | Jul 10 04:19:40 PM PDT 24 | 5092877 ps | ||
| T2 | /workspace/coverage/default/8.prim_esc_test.296241436 | Jul 10 04:19:38 PM PDT 24 | Jul 10 04:19:39 PM PDT 24 | 4592312 ps | ||
| T3 | /workspace/coverage/default/17.prim_esc_test.1897770955 | Jul 10 04:19:39 PM PDT 24 | Jul 10 04:19:41 PM PDT 24 | 4969068 ps | ||
| T13 | /workspace/coverage/default/0.prim_esc_test.3352409336 | Jul 10 04:19:38 PM PDT 24 | Jul 10 04:19:41 PM PDT 24 | 5091161 ps | ||
| T12 | /workspace/coverage/default/4.prim_esc_test.712916145 | Jul 10 04:19:35 PM PDT 24 | Jul 10 04:19:37 PM PDT 24 | 4402381 ps | ||
| T6 | /workspace/coverage/default/18.prim_esc_test.767422235 | Jul 10 04:19:48 PM PDT 24 | Jul 10 04:19:49 PM PDT 24 | 5030800 ps | ||
| T7 | /workspace/coverage/default/13.prim_esc_test.2151038507 | Jul 10 04:19:38 PM PDT 24 | Jul 10 04:19:40 PM PDT 24 | 4636522 ps | ||
| T9 | /workspace/coverage/default/12.prim_esc_test.1817138056 | Jul 10 04:19:39 PM PDT 24 | Jul 10 04:19:41 PM PDT 24 | 5148764 ps | ||
| T4 | /workspace/coverage/default/14.prim_esc_test.887930752 | Jul 10 04:19:38 PM PDT 24 | Jul 10 04:19:39 PM PDT 24 | 4644033 ps | ||
| T5 | /workspace/coverage/default/11.prim_esc_test.2922051947 | Jul 10 04:19:40 PM PDT 24 | Jul 10 04:19:41 PM PDT 24 | 5400945 ps | ||
| T14 | /workspace/coverage/default/3.prim_esc_test.1666545705 | Jul 10 04:19:37 PM PDT 24 | Jul 10 04:19:38 PM PDT 24 | 4937859 ps | ||
| T15 | /workspace/coverage/default/19.prim_esc_test.2476361531 | Jul 10 04:19:51 PM PDT 24 | Jul 10 04:19:53 PM PDT 24 | 5129259 ps | ||
| T16 | /workspace/coverage/default/1.prim_esc_test.1814977475 | Jul 10 04:19:31 PM PDT 24 | Jul 10 04:19:32 PM PDT 24 | 4996291 ps | ||
| T17 | /workspace/coverage/default/15.prim_esc_test.268597783 | Jul 10 04:19:44 PM PDT 24 | Jul 10 04:19:45 PM PDT 24 | 5066241 ps | ||
| T10 | /workspace/coverage/default/5.prim_esc_test.3962496406 | Jul 10 04:19:41 PM PDT 24 | Jul 10 04:19:43 PM PDT 24 | 4972004 ps | ||
| T18 | /workspace/coverage/default/7.prim_esc_test.1807612918 | Jul 10 04:19:31 PM PDT 24 | Jul 10 04:19:32 PM PDT 24 | 4505135 ps | ||
| T11 | /workspace/coverage/default/2.prim_esc_test.391926096 | Jul 10 04:19:40 PM PDT 24 | Jul 10 04:19:41 PM PDT 24 | 4302203 ps | ||
| T19 | /workspace/coverage/default/16.prim_esc_test.762681255 | Jul 10 04:19:31 PM PDT 24 | Jul 10 04:19:32 PM PDT 24 | 4730703 ps | ||
| T20 | /workspace/coverage/default/9.prim_esc_test.372649200 | Jul 10 04:19:39 PM PDT 24 | Jul 10 04:19:41 PM PDT 24 | 5257149 ps | ||
| T8 | /workspace/coverage/default/6.prim_esc_test.2964762350 | Jul 10 04:19:38 PM PDT 24 | Jul 10 04:19:40 PM PDT 24 | 5265998 ps |
| Test location | /workspace/coverage/default/18.prim_esc_test.767422235 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5030800 ps |
| CPU time | 0.41 seconds |
| Started | Jul 10 04:19:48 PM PDT 24 |
| Finished | Jul 10 04:19:49 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-448d4a50-d945-436c-9267-a0f842b4f054 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=767422235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.767422235 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1897770955 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4969068 ps |
| CPU time | 0.44 seconds |
| Started | Jul 10 04:19:39 PM PDT 24 |
| Finished | Jul 10 04:19:41 PM PDT 24 |
| Peak memory | 146436 kb |
| Host | smart-f5648719-fced-4515-b72f-d75967776fae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1897770955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1897770955 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.391926096 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4302203 ps |
| CPU time | 0.38 seconds |
| Started | Jul 10 04:19:40 PM PDT 24 |
| Finished | Jul 10 04:19:41 PM PDT 24 |
| Peak memory | 145512 kb |
| Host | smart-20f9a758-0a0d-4b56-ade9-94df95191eaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391926096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.391926096 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2151038507 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4636522 ps |
| CPU time | 0.38 seconds |
| Started | Jul 10 04:19:38 PM PDT 24 |
| Finished | Jul 10 04:19:40 PM PDT 24 |
| Peak memory | 146224 kb |
| Host | smart-b61266ea-b841-4bb3-8085-0db8ab662981 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2151038507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2151038507 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.887930752 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4644033 ps |
| CPU time | 0.37 seconds |
| Started | Jul 10 04:19:38 PM PDT 24 |
| Finished | Jul 10 04:19:39 PM PDT 24 |
| Peak memory | 146232 kb |
| Host | smart-1fbba651-db36-42ef-87bb-168cb68237cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=887930752 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.887930752 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3352409336 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5091161 ps |
| CPU time | 0.44 seconds |
| Started | Jul 10 04:19:38 PM PDT 24 |
| Finished | Jul 10 04:19:41 PM PDT 24 |
| Peak memory | 146384 kb |
| Host | smart-beb34453-12ed-4fef-a3e3-6721568ceac2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3352409336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3352409336 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.1814977475 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4996291 ps |
| CPU time | 0.41 seconds |
| Started | Jul 10 04:19:31 PM PDT 24 |
| Finished | Jul 10 04:19:32 PM PDT 24 |
| Peak memory | 144536 kb |
| Host | smart-c02b2e7f-0a96-45bc-8a72-a066690e239c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814977475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1814977475 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.818633312 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5092877 ps |
| CPU time | 0.39 seconds |
| Started | Jul 10 04:19:38 PM PDT 24 |
| Finished | Jul 10 04:19:40 PM PDT 24 |
| Peak memory | 146232 kb |
| Host | smart-6983463f-a319-4706-a68d-4d848aff406a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=818633312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.818633312 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2922051947 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5400945 ps |
| CPU time | 0.39 seconds |
| Started | Jul 10 04:19:40 PM PDT 24 |
| Finished | Jul 10 04:19:41 PM PDT 24 |
| Peak memory | 145568 kb |
| Host | smart-a302ec51-75c6-45d7-8ca7-bcdf7cbcd731 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2922051947 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2922051947 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1817138056 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5148764 ps |
| CPU time | 0.41 seconds |
| Started | Jul 10 04:19:39 PM PDT 24 |
| Finished | Jul 10 04:19:41 PM PDT 24 |
| Peak memory | 146228 kb |
| Host | smart-3d47cbf3-7a58-495e-9cab-709852e814f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1817138056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1817138056 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.268597783 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5066241 ps |
| CPU time | 0.36 seconds |
| Started | Jul 10 04:19:44 PM PDT 24 |
| Finished | Jul 10 04:19:45 PM PDT 24 |
| Peak memory | 146232 kb |
| Host | smart-a208ac55-55f8-433e-a42f-63e9d8e81b55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=268597783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.268597783 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.762681255 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4730703 ps |
| CPU time | 0.42 seconds |
| Started | Jul 10 04:19:31 PM PDT 24 |
| Finished | Jul 10 04:19:32 PM PDT 24 |
| Peak memory | 144832 kb |
| Host | smart-21f61b17-4f34-4ddf-86dc-047889f446c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762681255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.762681255 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2476361531 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5129259 ps |
| CPU time | 0.4 seconds |
| Started | Jul 10 04:19:51 PM PDT 24 |
| Finished | Jul 10 04:19:53 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-e0b1509e-a4b9-46b7-aeba-92e3b2cd89b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2476361531 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2476361531 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1666545705 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4937859 ps |
| CPU time | 0.39 seconds |
| Started | Jul 10 04:19:37 PM PDT 24 |
| Finished | Jul 10 04:19:38 PM PDT 24 |
| Peak memory | 146228 kb |
| Host | smart-4484c807-6793-49ac-841f-a16afb5e9d69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1666545705 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1666545705 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.712916145 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4402381 ps |
| CPU time | 0.48 seconds |
| Started | Jul 10 04:19:35 PM PDT 24 |
| Finished | Jul 10 04:19:37 PM PDT 24 |
| Peak memory | 146392 kb |
| Host | smart-48f591fc-f13b-4ff7-b08d-4be504b1a3a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712916145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.712916145 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3962496406 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4972004 ps |
| CPU time | 0.46 seconds |
| Started | Jul 10 04:19:41 PM PDT 24 |
| Finished | Jul 10 04:19:43 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-88589c12-3bd5-4157-a929-a5f4f449398a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962496406 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3962496406 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2964762350 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5265998 ps |
| CPU time | 0.39 seconds |
| Started | Jul 10 04:19:38 PM PDT 24 |
| Finished | Jul 10 04:19:40 PM PDT 24 |
| Peak memory | 146228 kb |
| Host | smart-626e4257-5a2f-4b55-b2d9-e911305d7cb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2964762350 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2964762350 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1807612918 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4505135 ps |
| CPU time | 0.39 seconds |
| Started | Jul 10 04:19:31 PM PDT 24 |
| Finished | Jul 10 04:19:32 PM PDT 24 |
| Peak memory | 145624 kb |
| Host | smart-62802520-2869-403b-a832-86d7f22fdb37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1807612918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1807612918 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.296241436 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4592312 ps |
| CPU time | 0.38 seconds |
| Started | Jul 10 04:19:38 PM PDT 24 |
| Finished | Jul 10 04:19:39 PM PDT 24 |
| Peak memory | 146232 kb |
| Host | smart-203afe2d-f35f-4d23-bf61-d40afcf6f44c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=296241436 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.296241436 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.372649200 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5257149 ps |
| CPU time | 0.38 seconds |
| Started | Jul 10 04:19:39 PM PDT 24 |
| Finished | Jul 10 04:19:41 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-dec169f6-741a-4264-97c4-c9a247b7bcc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=372649200 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.372649200 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |