Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.13 86.13 92.38 92.38 82.93 82.93 100.00 100.00 78.57 78.57 81.40 81.40 81.48 81.48 /workspace/coverage/default/1.prim_esc_test.2696411332
88.27 2.14 93.33 0.95 85.37 2.44 100.00 0.00 85.71 7.14 83.72 2.33 81.48 0.00 /workspace/coverage/default/15.prim_esc_test.3853429294
89.41 1.14 94.29 0.95 85.37 0.00 100.00 0.00 89.29 3.57 86.05 2.33 81.48 0.00 /workspace/coverage/default/10.prim_esc_test.2281927484
90.55 1.14 95.24 0.95 85.37 0.00 100.00 0.00 92.86 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/13.prim_esc_test.1538329805
91.15 0.60 95.24 0.00 85.37 0.00 100.00 0.00 96.43 3.57 88.37 0.00 81.48 0.00 /workspace/coverage/default/11.prim_esc_test.2857317725

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.3343184669
/workspace/coverage/default/12.prim_esc_test.512259820
/workspace/coverage/default/14.prim_esc_test.2917322235
/workspace/coverage/default/16.prim_esc_test.1528799386
/workspace/coverage/default/17.prim_esc_test.4258487526
/workspace/coverage/default/18.prim_esc_test.2307783715
/workspace/coverage/default/19.prim_esc_test.3047264634
/workspace/coverage/default/2.prim_esc_test.907421578
/workspace/coverage/default/3.prim_esc_test.3746787033
/workspace/coverage/default/4.prim_esc_test.363854651
/workspace/coverage/default/5.prim_esc_test.2670350988
/workspace/coverage/default/6.prim_esc_test.387309608
/workspace/coverage/default/7.prim_esc_test.3760971695
/workspace/coverage/default/8.prim_esc_test.3760339327
/workspace/coverage/default/9.prim_esc_test.2735791



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/12.prim_esc_test.512259820 Jul 11 04:25:54 PM PDT 24 Jul 11 04:25:56 PM PDT 24 4670091 ps
T2 /workspace/coverage/default/15.prim_esc_test.3853429294 Jul 11 04:25:54 PM PDT 24 Jul 11 04:25:56 PM PDT 24 4789217 ps
T3 /workspace/coverage/default/9.prim_esc_test.2735791 Jul 11 04:26:58 PM PDT 24 Jul 11 04:27:00 PM PDT 24 4924587 ps
T4 /workspace/coverage/default/4.prim_esc_test.363854651 Jul 11 04:25:36 PM PDT 24 Jul 11 04:25:38 PM PDT 24 4833395 ps
T5 /workspace/coverage/default/1.prim_esc_test.2696411332 Jul 11 04:25:30 PM PDT 24 Jul 11 04:25:33 PM PDT 24 4486537 ps
T15 /workspace/coverage/default/11.prim_esc_test.2857317725 Jul 11 04:26:58 PM PDT 24 Jul 11 04:27:00 PM PDT 24 4589132 ps
T6 /workspace/coverage/default/3.prim_esc_test.3746787033 Jul 11 04:27:10 PM PDT 24 Jul 11 04:27:13 PM PDT 24 4712896 ps
T16 /workspace/coverage/default/14.prim_esc_test.2917322235 Jul 11 04:25:47 PM PDT 24 Jul 11 04:25:49 PM PDT 24 5204059 ps
T7 /workspace/coverage/default/19.prim_esc_test.3047264634 Jul 11 04:25:54 PM PDT 24 Jul 11 04:25:56 PM PDT 24 5217463 ps
T17 /workspace/coverage/default/0.prim_esc_test.3343184669 Jul 11 04:26:58 PM PDT 24 Jul 11 04:27:00 PM PDT 24 5062206 ps
T9 /workspace/coverage/default/10.prim_esc_test.2281927484 Jul 11 04:25:35 PM PDT 24 Jul 11 04:25:36 PM PDT 24 4959081 ps
T10 /workspace/coverage/default/16.prim_esc_test.1528799386 Jul 11 04:25:54 PM PDT 24 Jul 11 04:25:56 PM PDT 24 5194420 ps
T12 /workspace/coverage/default/18.prim_esc_test.2307783715 Jul 11 04:25:46 PM PDT 24 Jul 11 04:25:47 PM PDT 24 4800058 ps
T8 /workspace/coverage/default/17.prim_esc_test.4258487526 Jul 11 04:26:00 PM PDT 24 Jul 11 04:26:03 PM PDT 24 4396119 ps
T18 /workspace/coverage/default/6.prim_esc_test.387309608 Jul 11 04:25:35 PM PDT 24 Jul 11 04:25:37 PM PDT 24 4512887 ps
T13 /workspace/coverage/default/7.prim_esc_test.3760971695 Jul 11 04:25:36 PM PDT 24 Jul 11 04:25:38 PM PDT 24 4889852 ps
T11 /workspace/coverage/default/5.prim_esc_test.2670350988 Jul 11 04:25:35 PM PDT 24 Jul 11 04:25:37 PM PDT 24 5008796 ps
T14 /workspace/coverage/default/2.prim_esc_test.907421578 Jul 11 04:25:29 PM PDT 24 Jul 11 04:25:32 PM PDT 24 4322646 ps
T19 /workspace/coverage/default/13.prim_esc_test.1538329805 Jul 11 04:25:54 PM PDT 24 Jul 11 04:25:56 PM PDT 24 4931496 ps
T20 /workspace/coverage/default/8.prim_esc_test.3760339327 Jul 11 04:26:57 PM PDT 24 Jul 11 04:26:58 PM PDT 24 5080721 ps

Test location /workspace/coverage/default/1.prim_esc_test.2696411332
Short name T5
Test name
Test status
Simulation time 4486537 ps
CPU time 0.39 seconds
Started Jul 11 04:25:30 PM PDT 24
Finished Jul 11 04:25:33 PM PDT 24
Peak memory 146044 kb
Host smart-7f3146a8-3763-4c39-930a-1b1cee40ba6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696411332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2696411332
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.3853429294
Short name T2
Test name
Test status
Simulation time 4789217 ps
CPU time 0.42 seconds
Started Jul 11 04:25:54 PM PDT 24
Finished Jul 11 04:25:56 PM PDT 24
Peak memory 146316 kb
Host smart-1427d184-430b-4e5c-a913-825759827a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853429294 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3853429294
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.2281927484
Short name T9
Test name
Test status
Simulation time 4959081 ps
CPU time 0.38 seconds
Started Jul 11 04:25:35 PM PDT 24
Finished Jul 11 04:25:36 PM PDT 24
Peak memory 146044 kb
Host smart-b16b444a-f141-40c9-abda-46cd8da161d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281927484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2281927484
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.1538329805
Short name T19
Test name
Test status
Simulation time 4931496 ps
CPU time 0.39 seconds
Started Jul 11 04:25:54 PM PDT 24
Finished Jul 11 04:25:56 PM PDT 24
Peak memory 146312 kb
Host smart-6193bbe4-718e-4fb3-b326-adaa8f74159b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538329805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1538329805
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.2857317725
Short name T15
Test name
Test status
Simulation time 4589132 ps
CPU time 0.36 seconds
Started Jul 11 04:26:58 PM PDT 24
Finished Jul 11 04:27:00 PM PDT 24
Peak memory 145760 kb
Host smart-53bfbc51-a8c2-4425-9009-5dfaaf2c9048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857317725 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2857317725
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.3343184669
Short name T17
Test name
Test status
Simulation time 5062206 ps
CPU time 0.37 seconds
Started Jul 11 04:26:58 PM PDT 24
Finished Jul 11 04:27:00 PM PDT 24
Peak memory 145740 kb
Host smart-a2fbe432-366c-4d2d-90c6-645fec6356fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343184669 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3343184669
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.512259820
Short name T1
Test name
Test status
Simulation time 4670091 ps
CPU time 0.39 seconds
Started Jul 11 04:25:54 PM PDT 24
Finished Jul 11 04:25:56 PM PDT 24
Peak memory 146296 kb
Host smart-46df8f28-ea10-40c8-8dc0-3f8b312d1d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512259820 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.512259820
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.2917322235
Short name T16
Test name
Test status
Simulation time 5204059 ps
CPU time 0.39 seconds
Started Jul 11 04:25:47 PM PDT 24
Finished Jul 11 04:25:49 PM PDT 24
Peak memory 146044 kb
Host smart-b4379a60-5b41-4e26-bbcf-9040b4b356cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917322235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2917322235
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1528799386
Short name T10
Test name
Test status
Simulation time 5194420 ps
CPU time 0.39 seconds
Started Jul 11 04:25:54 PM PDT 24
Finished Jul 11 04:25:56 PM PDT 24
Peak memory 146268 kb
Host smart-7986c765-927a-4c3a-8dcb-b2a8c6baf0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528799386 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1528799386
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.4258487526
Short name T8
Test name
Test status
Simulation time 4396119 ps
CPU time 0.41 seconds
Started Jul 11 04:26:00 PM PDT 24
Finished Jul 11 04:26:03 PM PDT 24
Peak memory 145980 kb
Host smart-d5a200cb-5b63-4676-97f0-d7cf4ddbc8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258487526 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.4258487526
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.2307783715
Short name T12
Test name
Test status
Simulation time 4800058 ps
CPU time 0.4 seconds
Started Jul 11 04:25:46 PM PDT 24
Finished Jul 11 04:25:47 PM PDT 24
Peak memory 145980 kb
Host smart-c7938f23-f031-4585-a435-164185e666b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307783715 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2307783715
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.3047264634
Short name T7
Test name
Test status
Simulation time 5217463 ps
CPU time 0.43 seconds
Started Jul 11 04:25:54 PM PDT 24
Finished Jul 11 04:25:56 PM PDT 24
Peak memory 146304 kb
Host smart-68ef4d4f-379b-420b-9f7d-d46441c4d921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047264634 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3047264634
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.907421578
Short name T14
Test name
Test status
Simulation time 4322646 ps
CPU time 0.44 seconds
Started Jul 11 04:25:29 PM PDT 24
Finished Jul 11 04:25:32 PM PDT 24
Peak memory 146048 kb
Host smart-3b4d41a8-d530-4e47-a4bb-4390af10313c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907421578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.907421578
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.3746787033
Short name T6
Test name
Test status
Simulation time 4712896 ps
CPU time 0.38 seconds
Started Jul 11 04:27:10 PM PDT 24
Finished Jul 11 04:27:13 PM PDT 24
Peak memory 145940 kb
Host smart-c300120f-7cf4-45a9-8961-7c3ee0570f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746787033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3746787033
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.363854651
Short name T4
Test name
Test status
Simulation time 4833395 ps
CPU time 0.43 seconds
Started Jul 11 04:25:36 PM PDT 24
Finished Jul 11 04:25:38 PM PDT 24
Peak memory 146312 kb
Host smart-1dc296bf-6cbe-4192-a3a4-9ff9f44844af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363854651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.363854651
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.2670350988
Short name T11
Test name
Test status
Simulation time 5008796 ps
CPU time 0.39 seconds
Started Jul 11 04:25:35 PM PDT 24
Finished Jul 11 04:25:37 PM PDT 24
Peak memory 145436 kb
Host smart-25db3b03-8c2f-410c-a451-e75792b3e2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670350988 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2670350988
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.387309608
Short name T18
Test name
Test status
Simulation time 4512887 ps
CPU time 0.37 seconds
Started Jul 11 04:25:35 PM PDT 24
Finished Jul 11 04:25:37 PM PDT 24
Peak memory 145412 kb
Host smart-4147dfef-ead1-49e8-af7e-3306a187a01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387309608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.387309608
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.3760971695
Short name T13
Test name
Test status
Simulation time 4889852 ps
CPU time 0.38 seconds
Started Jul 11 04:25:36 PM PDT 24
Finished Jul 11 04:25:38 PM PDT 24
Peak memory 146044 kb
Host smart-5be1b4f6-23ad-4337-9e38-c48371d2ddd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760971695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3760971695
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.3760339327
Short name T20
Test name
Test status
Simulation time 5080721 ps
CPU time 0.4 seconds
Started Jul 11 04:26:57 PM PDT 24
Finished Jul 11 04:26:58 PM PDT 24
Peak memory 144944 kb
Host smart-f57cb599-3ffc-4864-bc2f-6919650ea0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760339327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3760339327
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.2735791
Short name T3
Test name
Test status
Simulation time 4924587 ps
CPU time 0.36 seconds
Started Jul 11 04:26:58 PM PDT 24
Finished Jul 11 04:27:00 PM PDT 24
Peak memory 145736 kb
Host smart-c79c4044-0078-4d76-8ef9-18466a4fa897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2735791
Directory /workspace/9.prim_esc_test/latest
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