Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.23 85.23 90.48 90.48 85.37 85.37 100.00 100.00 75.00 75.00 79.07 79.07 81.48 81.48 /workspace/coverage/default/12.prim_esc_test.938990048
88.27 3.04 93.33 2.86 85.37 0.00 100.00 0.00 85.71 10.71 83.72 4.65 81.48 0.00 /workspace/coverage/default/4.prim_esc_test.3440532946
90.01 1.74 94.29 0.95 85.37 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/1.prim_esc_test.497832459
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/0.prim_esc_test.2818359739

Tests that do not contribute to grading

Name
/workspace/coverage/default/10.prim_esc_test.2392921822
/workspace/coverage/default/11.prim_esc_test.564201298
/workspace/coverage/default/13.prim_esc_test.167588492
/workspace/coverage/default/14.prim_esc_test.1183325168
/workspace/coverage/default/15.prim_esc_test.1352763242
/workspace/coverage/default/16.prim_esc_test.720488323
/workspace/coverage/default/17.prim_esc_test.1949229635
/workspace/coverage/default/18.prim_esc_test.2704782183
/workspace/coverage/default/19.prim_esc_test.3893000223
/workspace/coverage/default/2.prim_esc_test.1579402103
/workspace/coverage/default/3.prim_esc_test.2074462593
/workspace/coverage/default/5.prim_esc_test.2787842765
/workspace/coverage/default/6.prim_esc_test.4287375103
/workspace/coverage/default/7.prim_esc_test.3774629616
/workspace/coverage/default/8.prim_esc_test.2522337373
/workspace/coverage/default/9.prim_esc_test.2832619020



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/12.prim_esc_test.938990048 Jul 12 04:41:53 PM PDT 24 Jul 12 04:41:55 PM PDT 24 4821450 ps
T2 /workspace/coverage/default/2.prim_esc_test.1579402103 Jul 12 04:41:51 PM PDT 24 Jul 12 04:41:52 PM PDT 24 4612909 ps
T3 /workspace/coverage/default/6.prim_esc_test.4287375103 Jul 12 04:42:00 PM PDT 24 Jul 12 04:42:02 PM PDT 24 5357389 ps
T13 /workspace/coverage/default/14.prim_esc_test.1183325168 Jul 12 04:41:53 PM PDT 24 Jul 12 04:41:54 PM PDT 24 5352023 ps
T6 /workspace/coverage/default/19.prim_esc_test.3893000223 Jul 12 04:41:59 PM PDT 24 Jul 12 04:42:01 PM PDT 24 5095895 ps
T11 /workspace/coverage/default/18.prim_esc_test.2704782183 Jul 12 04:42:00 PM PDT 24 Jul 12 04:42:02 PM PDT 24 4830110 ps
T4 /workspace/coverage/default/1.prim_esc_test.497832459 Jul 12 04:41:53 PM PDT 24 Jul 12 04:41:55 PM PDT 24 4915401 ps
T5 /workspace/coverage/default/10.prim_esc_test.2392921822 Jul 12 04:41:54 PM PDT 24 Jul 12 04:41:55 PM PDT 24 5278763 ps
T10 /workspace/coverage/default/5.prim_esc_test.2787842765 Jul 12 04:41:55 PM PDT 24 Jul 12 04:41:56 PM PDT 24 5133428 ps
T14 /workspace/coverage/default/9.prim_esc_test.2832619020 Jul 12 04:41:52 PM PDT 24 Jul 12 04:41:53 PM PDT 24 4915936 ps
T16 /workspace/coverage/default/13.prim_esc_test.167588492 Jul 12 04:41:54 PM PDT 24 Jul 12 04:41:55 PM PDT 24 5325120 ps
T7 /workspace/coverage/default/8.prim_esc_test.2522337373 Jul 12 04:41:54 PM PDT 24 Jul 12 04:41:55 PM PDT 24 5088931 ps
T17 /workspace/coverage/default/3.prim_esc_test.2074462593 Jul 12 04:41:54 PM PDT 24 Jul 12 04:41:55 PM PDT 24 4904038 ps
T8 /workspace/coverage/default/4.prim_esc_test.3440532946 Jul 12 04:41:55 PM PDT 24 Jul 12 04:41:56 PM PDT 24 5061895 ps
T18 /workspace/coverage/default/0.prim_esc_test.2818359739 Jul 12 04:41:46 PM PDT 24 Jul 12 04:41:47 PM PDT 24 4790169 ps
T19 /workspace/coverage/default/11.prim_esc_test.564201298 Jul 12 04:41:59 PM PDT 24 Jul 12 04:42:02 PM PDT 24 5201035 ps
T15 /workspace/coverage/default/15.prim_esc_test.1352763242 Jul 12 04:41:57 PM PDT 24 Jul 12 04:41:58 PM PDT 24 5037229 ps
T12 /workspace/coverage/default/16.prim_esc_test.720488323 Jul 12 04:41:53 PM PDT 24 Jul 12 04:41:54 PM PDT 24 5189683 ps
T9 /workspace/coverage/default/7.prim_esc_test.3774629616 Jul 12 04:41:53 PM PDT 24 Jul 12 04:41:55 PM PDT 24 4636168 ps
T20 /workspace/coverage/default/17.prim_esc_test.1949229635 Jul 12 04:41:53 PM PDT 24 Jul 12 04:41:55 PM PDT 24 5038781 ps

Test location /workspace/coverage/default/12.prim_esc_test.938990048
Short name T1
Test name
Test status
Simulation time 4821450 ps
CPU time 0.37 seconds
Started Jul 12 04:41:53 PM PDT 24
Finished Jul 12 04:41:55 PM PDT 24
Peak memory 146024 kb
Host smart-6dace579-60ec-4581-9e9a-00d0949b1e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938990048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.938990048
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.3440532946
Short name T8
Test name
Test status
Simulation time 5061895 ps
CPU time 0.37 seconds
Started Jul 12 04:41:55 PM PDT 24
Finished Jul 12 04:41:56 PM PDT 24
Peak memory 146044 kb
Host smart-6f73d9f1-6630-406c-b938-f639049b2516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440532946 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3440532946
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.497832459
Short name T4
Test name
Test status
Simulation time 4915401 ps
CPU time 0.39 seconds
Started Jul 12 04:41:53 PM PDT 24
Finished Jul 12 04:41:55 PM PDT 24
Peak memory 146128 kb
Host smart-8f3c77b9-6d85-482d-8cd7-4d483b1c2ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497832459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.497832459
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.2818359739
Short name T18
Test name
Test status
Simulation time 4790169 ps
CPU time 0.39 seconds
Started Jul 12 04:41:46 PM PDT 24
Finished Jul 12 04:41:47 PM PDT 24
Peak memory 146060 kb
Host smart-d6c29f87-a64c-4665-8ac9-48b67376495d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818359739 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2818359739
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.2392921822
Short name T5
Test name
Test status
Simulation time 5278763 ps
CPU time 0.37 seconds
Started Jul 12 04:41:54 PM PDT 24
Finished Jul 12 04:41:55 PM PDT 24
Peak memory 146116 kb
Host smart-40c7535d-cea6-4250-a82e-2250bb3b4252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392921822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2392921822
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.564201298
Short name T19
Test name
Test status
Simulation time 5201035 ps
CPU time 0.41 seconds
Started Jul 12 04:41:59 PM PDT 24
Finished Jul 12 04:42:02 PM PDT 24
Peak memory 146072 kb
Host smart-0b72f607-021d-45d8-8f90-65a2dcffde27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564201298 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.564201298
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.167588492
Short name T16
Test name
Test status
Simulation time 5325120 ps
CPU time 0.36 seconds
Started Jul 12 04:41:54 PM PDT 24
Finished Jul 12 04:41:55 PM PDT 24
Peak memory 146112 kb
Host smart-8bca4a12-c2e5-4f34-9081-f8ad2785ead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167588492 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.167588492
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.1183325168
Short name T13
Test name
Test status
Simulation time 5352023 ps
CPU time 0.4 seconds
Started Jul 12 04:41:53 PM PDT 24
Finished Jul 12 04:41:54 PM PDT 24
Peak memory 146108 kb
Host smart-c4d98212-8969-4c78-ad8a-e06ab12f3126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183325168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1183325168
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.1352763242
Short name T15
Test name
Test status
Simulation time 5037229 ps
CPU time 0.42 seconds
Started Jul 12 04:41:57 PM PDT 24
Finished Jul 12 04:41:58 PM PDT 24
Peak memory 146084 kb
Host smart-56d07788-dfe0-4f51-827d-d873bc462af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352763242 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1352763242
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.720488323
Short name T12
Test name
Test status
Simulation time 5189683 ps
CPU time 0.38 seconds
Started Jul 12 04:41:53 PM PDT 24
Finished Jul 12 04:41:54 PM PDT 24
Peak memory 146052 kb
Host smart-719dd752-da16-460b-9533-7180ebd511f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720488323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.720488323
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.1949229635
Short name T20
Test name
Test status
Simulation time 5038781 ps
CPU time 0.38 seconds
Started Jul 12 04:41:53 PM PDT 24
Finished Jul 12 04:41:55 PM PDT 24
Peak memory 146164 kb
Host smart-4881cb64-8c2e-4edf-b4bf-265353958d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949229635 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1949229635
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.2704782183
Short name T11
Test name
Test status
Simulation time 4830110 ps
CPU time 0.39 seconds
Started Jul 12 04:42:00 PM PDT 24
Finished Jul 12 04:42:02 PM PDT 24
Peak memory 146084 kb
Host smart-21d797e8-309e-431d-b2fa-c90c609592e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704782183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2704782183
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.3893000223
Short name T6
Test name
Test status
Simulation time 5095895 ps
CPU time 0.36 seconds
Started Jul 12 04:41:59 PM PDT 24
Finished Jul 12 04:42:01 PM PDT 24
Peak memory 146108 kb
Host smart-ce1de897-a3b7-4af8-b40f-bdeb718e627a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893000223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3893000223
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.1579402103
Short name T2
Test name
Test status
Simulation time 4612909 ps
CPU time 0.38 seconds
Started Jul 12 04:41:51 PM PDT 24
Finished Jul 12 04:41:52 PM PDT 24
Peak memory 145980 kb
Host smart-6e374865-f571-44e3-bd8f-8da1ab1a712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579402103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1579402103
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.2074462593
Short name T17
Test name
Test status
Simulation time 4904038 ps
CPU time 0.38 seconds
Started Jul 12 04:41:54 PM PDT 24
Finished Jul 12 04:41:55 PM PDT 24
Peak memory 145976 kb
Host smart-10780f57-d955-45ad-9025-92cfb1c33234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074462593 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2074462593
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.2787842765
Short name T10
Test name
Test status
Simulation time 5133428 ps
CPU time 0.38 seconds
Started Jul 12 04:41:55 PM PDT 24
Finished Jul 12 04:41:56 PM PDT 24
Peak memory 146044 kb
Host smart-8ae04a77-5ee8-48cc-b03f-aa827178c125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787842765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2787842765
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.4287375103
Short name T3
Test name
Test status
Simulation time 5357389 ps
CPU time 0.37 seconds
Started Jul 12 04:42:00 PM PDT 24
Finished Jul 12 04:42:02 PM PDT 24
Peak memory 146004 kb
Host smart-ec80e542-e4a2-4d5e-82af-a69589399870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287375103 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4287375103
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.3774629616
Short name T9
Test name
Test status
Simulation time 4636168 ps
CPU time 0.38 seconds
Started Jul 12 04:41:53 PM PDT 24
Finished Jul 12 04:41:55 PM PDT 24
Peak memory 145940 kb
Host smart-99457c03-b3a9-40df-a321-d66bb9dd8026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774629616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3774629616
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.2522337373
Short name T7
Test name
Test status
Simulation time 5088931 ps
CPU time 0.37 seconds
Started Jul 12 04:41:54 PM PDT 24
Finished Jul 12 04:41:55 PM PDT 24
Peak memory 145940 kb
Host smart-93f191a6-cee5-4b5f-aef4-92c09e1f659e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522337373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2522337373
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.2832619020
Short name T14
Test name
Test status
Simulation time 4915936 ps
CPU time 0.39 seconds
Started Jul 12 04:41:52 PM PDT 24
Finished Jul 12 04:41:53 PM PDT 24
Peak memory 146060 kb
Host smart-87664915-11a6-4379-ab32-a001c8cb52e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832619020 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2832619020
Directory /workspace/9.prim_esc_test/latest
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