Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.12 85.12 92.38 92.38 80.49 80.49 100.00 100.00 75.00 75.00 81.40 81.40 81.48 81.48 /workspace/coverage/default/1.prim_esc_test.360232918
88.27 3.15 93.33 0.95 85.37 4.88 100.00 0.00 85.71 10.71 83.72 2.33 81.48 0.00 /workspace/coverage/default/15.prim_esc_test.3895733407
90.01 1.74 94.29 0.95 85.37 0.00 100.00 0.00 92.86 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/19.prim_esc_test.979961438
91.15 1.14 95.24 0.95 85.37 0.00 100.00 0.00 96.43 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/5.prim_esc_test.508553408

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.2567984801
/workspace/coverage/default/10.prim_esc_test.417705355
/workspace/coverage/default/11.prim_esc_test.1737826
/workspace/coverage/default/12.prim_esc_test.771693754
/workspace/coverage/default/13.prim_esc_test.2584755914
/workspace/coverage/default/14.prim_esc_test.1034309274
/workspace/coverage/default/16.prim_esc_test.2156691636
/workspace/coverage/default/17.prim_esc_test.3252518301
/workspace/coverage/default/18.prim_esc_test.729513497
/workspace/coverage/default/2.prim_esc_test.3762484744
/workspace/coverage/default/3.prim_esc_test.355035757
/workspace/coverage/default/4.prim_esc_test.2278641021
/workspace/coverage/default/6.prim_esc_test.499808533
/workspace/coverage/default/7.prim_esc_test.4291467676
/workspace/coverage/default/8.prim_esc_test.3395593167
/workspace/coverage/default/9.prim_esc_test.1116090462



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/9.prim_esc_test.1116090462 Jul 13 04:25:28 PM PDT 24 Jul 13 04:25:29 PM PDT 24 4807498 ps
T2 /workspace/coverage/default/15.prim_esc_test.3895733407 Jul 13 04:23:35 PM PDT 24 Jul 13 04:23:36 PM PDT 24 4640177 ps
T3 /workspace/coverage/default/12.prim_esc_test.771693754 Jul 13 04:25:06 PM PDT 24 Jul 13 04:25:07 PM PDT 24 4992078 ps
T14 /workspace/coverage/default/7.prim_esc_test.4291467676 Jul 13 04:25:36 PM PDT 24 Jul 13 04:25:37 PM PDT 24 5306025 ps
T7 /workspace/coverage/default/5.prim_esc_test.508553408 Jul 13 04:23:34 PM PDT 24 Jul 13 04:23:34 PM PDT 24 4311847 ps
T4 /workspace/coverage/default/19.prim_esc_test.979961438 Jul 13 04:24:33 PM PDT 24 Jul 13 04:24:34 PM PDT 24 4636660 ps
T5 /workspace/coverage/default/6.prim_esc_test.499808533 Jul 13 04:25:42 PM PDT 24 Jul 13 04:25:43 PM PDT 24 5265360 ps
T6 /workspace/coverage/default/10.prim_esc_test.417705355 Jul 13 04:25:30 PM PDT 24 Jul 13 04:25:31 PM PDT 24 4403264 ps
T10 /workspace/coverage/default/2.prim_esc_test.3762484744 Jul 13 04:25:11 PM PDT 24 Jul 13 04:25:14 PM PDT 24 4517981 ps
T11 /workspace/coverage/default/1.prim_esc_test.360232918 Jul 13 04:19:38 PM PDT 24 Jul 13 04:19:40 PM PDT 24 5016675 ps
T13 /workspace/coverage/default/11.prim_esc_test.1737826 Jul 13 04:22:30 PM PDT 24 Jul 13 04:22:31 PM PDT 24 4797203 ps
T8 /workspace/coverage/default/18.prim_esc_test.729513497 Jul 13 04:22:34 PM PDT 24 Jul 13 04:22:34 PM PDT 24 4267780 ps
T15 /workspace/coverage/default/13.prim_esc_test.2584755914 Jul 13 04:19:49 PM PDT 24 Jul 13 04:19:50 PM PDT 24 4585933 ps
T16 /workspace/coverage/default/16.prim_esc_test.2156691636 Jul 13 04:22:49 PM PDT 24 Jul 13 04:22:50 PM PDT 24 4895412 ps
T17 /workspace/coverage/default/17.prim_esc_test.3252518301 Jul 13 04:25:30 PM PDT 24 Jul 13 04:25:31 PM PDT 24 4773913 ps
T9 /workspace/coverage/default/0.prim_esc_test.2567984801 Jul 13 04:25:30 PM PDT 24 Jul 13 04:25:31 PM PDT 24 4797349 ps
T18 /workspace/coverage/default/8.prim_esc_test.3395593167 Jul 13 04:25:22 PM PDT 24 Jul 13 04:25:22 PM PDT 24 4659635 ps
T19 /workspace/coverage/default/3.prim_esc_test.355035757 Jul 13 04:25:23 PM PDT 24 Jul 13 04:25:24 PM PDT 24 4581793 ps
T12 /workspace/coverage/default/14.prim_esc_test.1034309274 Jul 13 04:25:07 PM PDT 24 Jul 13 04:25:08 PM PDT 24 4725436 ps
T20 /workspace/coverage/default/4.prim_esc_test.2278641021 Jul 13 04:20:12 PM PDT 24 Jul 13 04:20:13 PM PDT 24 4767017 ps

Test location /workspace/coverage/default/1.prim_esc_test.360232918
Short name T11
Test name
Test status
Simulation time 5016675 ps
CPU time 0.48 seconds
Started Jul 13 04:19:38 PM PDT 24
Finished Jul 13 04:19:40 PM PDT 24
Peak memory 146360 kb
Host smart-355a48ca-b376-4ce2-9bea-02849adbf2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360232918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.360232918
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.3895733407
Short name T2
Test name
Test status
Simulation time 4640177 ps
CPU time 0.4 seconds
Started Jul 13 04:23:35 PM PDT 24
Finished Jul 13 04:23:36 PM PDT 24
Peak memory 145812 kb
Host smart-5ecfd16d-a6fd-46a7-b733-f633ffb56f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895733407 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3895733407
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.979961438
Short name T4
Test name
Test status
Simulation time 4636660 ps
CPU time 0.41 seconds
Started Jul 13 04:24:33 PM PDT 24
Finished Jul 13 04:24:34 PM PDT 24
Peak memory 146104 kb
Host smart-6cb6fc90-13d2-4e7a-a301-d2944e4d539e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979961438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.979961438
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.508553408
Short name T7
Test name
Test status
Simulation time 4311847 ps
CPU time 0.39 seconds
Started Jul 13 04:23:34 PM PDT 24
Finished Jul 13 04:23:34 PM PDT 24
Peak memory 145816 kb
Host smart-b6dbd182-51cd-4d7b-b430-2afb95bbd210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508553408 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.508553408
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.2567984801
Short name T9
Test name
Test status
Simulation time 4797349 ps
CPU time 0.39 seconds
Started Jul 13 04:25:30 PM PDT 24
Finished Jul 13 04:25:31 PM PDT 24
Peak memory 146332 kb
Host smart-bdddc74b-256d-4915-998d-5f871d2f1396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567984801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2567984801
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.417705355
Short name T6
Test name
Test status
Simulation time 4403264 ps
CPU time 0.38 seconds
Started Jul 13 04:25:30 PM PDT 24
Finished Jul 13 04:25:31 PM PDT 24
Peak memory 145404 kb
Host smart-201bc059-884a-4018-ab08-6ec95e4402c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417705355 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.417705355
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.1737826
Short name T13
Test name
Test status
Simulation time 4797203 ps
CPU time 0.4 seconds
Started Jul 13 04:22:30 PM PDT 24
Finished Jul 13 04:22:31 PM PDT 24
Peak memory 145848 kb
Host smart-5510bb61-9ba7-409d-9b4a-4b9fa850ac13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737826 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1737826
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.771693754
Short name T3
Test name
Test status
Simulation time 4992078 ps
CPU time 0.45 seconds
Started Jul 13 04:25:06 PM PDT 24
Finished Jul 13 04:25:07 PM PDT 24
Peak memory 145716 kb
Host smart-7fec1481-5207-47c1-bbcf-8b0240faec48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771693754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.771693754
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.2584755914
Short name T15
Test name
Test status
Simulation time 4585933 ps
CPU time 0.39 seconds
Started Jul 13 04:19:49 PM PDT 24
Finished Jul 13 04:19:50 PM PDT 24
Peak memory 145716 kb
Host smart-33b95fc1-e4ee-4ab7-9375-f8123d25fd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584755914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2584755914
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.1034309274
Short name T12
Test name
Test status
Simulation time 4725436 ps
CPU time 0.38 seconds
Started Jul 13 04:25:07 PM PDT 24
Finished Jul 13 04:25:08 PM PDT 24
Peak memory 145752 kb
Host smart-be5580bb-d87e-451c-bd30-d6a4583ccc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034309274 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1034309274
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.2156691636
Short name T16
Test name
Test status
Simulation time 4895412 ps
CPU time 0.43 seconds
Started Jul 13 04:22:49 PM PDT 24
Finished Jul 13 04:22:50 PM PDT 24
Peak memory 145772 kb
Host smart-ba1cba3e-6870-49b4-808a-a24763dd7f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156691636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2156691636
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.3252518301
Short name T17
Test name
Test status
Simulation time 4773913 ps
CPU time 0.38 seconds
Started Jul 13 04:25:30 PM PDT 24
Finished Jul 13 04:25:31 PM PDT 24
Peak memory 145348 kb
Host smart-3d68b6dd-9d92-401a-9198-bdcb5f132edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252518301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3252518301
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.729513497
Short name T8
Test name
Test status
Simulation time 4267780 ps
CPU time 0.39 seconds
Started Jul 13 04:22:34 PM PDT 24
Finished Jul 13 04:22:34 PM PDT 24
Peak memory 145880 kb
Host smart-0e8d5c03-0536-40fa-b480-c9a38a70cc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729513497 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.729513497
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.3762484744
Short name T10
Test name
Test status
Simulation time 4517981 ps
CPU time 0.43 seconds
Started Jul 13 04:25:11 PM PDT 24
Finished Jul 13 04:25:14 PM PDT 24
Peak memory 146388 kb
Host smart-deef465d-6bc8-44d2-b1a6-e676de8ee5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762484744 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3762484744
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.355035757
Short name T19
Test name
Test status
Simulation time 4581793 ps
CPU time 0.39 seconds
Started Jul 13 04:25:23 PM PDT 24
Finished Jul 13 04:25:24 PM PDT 24
Peak memory 145780 kb
Host smart-fdb85e91-bcf8-4cf0-844e-70a4a1a26918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355035757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.355035757
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.2278641021
Short name T20
Test name
Test status
Simulation time 4767017 ps
CPU time 0.4 seconds
Started Jul 13 04:20:12 PM PDT 24
Finished Jul 13 04:20:13 PM PDT 24
Peak memory 145716 kb
Host smart-41ba5f5d-e1be-476f-95de-ada352b12a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278641021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2278641021
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.499808533
Short name T5
Test name
Test status
Simulation time 5265360 ps
CPU time 0.39 seconds
Started Jul 13 04:25:42 PM PDT 24
Finished Jul 13 04:25:43 PM PDT 24
Peak memory 145688 kb
Host smart-64fc21d9-bdc3-4ec0-9693-9d8e78507216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499808533 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.499808533
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.4291467676
Short name T14
Test name
Test status
Simulation time 5306025 ps
CPU time 0.4 seconds
Started Jul 13 04:25:36 PM PDT 24
Finished Jul 13 04:25:37 PM PDT 24
Peak memory 145768 kb
Host smart-d49c8b73-33e3-4f3c-8e69-bcce501838f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291467676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4291467676
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.3395593167
Short name T18
Test name
Test status
Simulation time 4659635 ps
CPU time 0.42 seconds
Started Jul 13 04:25:22 PM PDT 24
Finished Jul 13 04:25:22 PM PDT 24
Peak memory 145768 kb
Host smart-bf46b206-193c-4f50-a99c-553dff3c5792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395593167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3395593167
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.1116090462
Short name T1
Test name
Test status
Simulation time 4807498 ps
CPU time 0.41 seconds
Started Jul 13 04:25:28 PM PDT 24
Finished Jul 13 04:25:29 PM PDT 24
Peak memory 146368 kb
Host smart-e6a5ace3-747c-48e1-a042-05e10b0e0abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116090462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1116090462
Directory /workspace/9.prim_esc_test/latest
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