| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.53 | 86.53 | 92.38 | 92.38 | 85.37 | 85.37 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/1.prim_esc_test.2056394078 |
| 88.27 | 1.74 | 93.33 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/15.prim_esc_test.3096445490 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/16.prim_esc_test.136761559 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.3006504585 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2813480425 |
| /workspace/coverage/default/11.prim_esc_test.2607885475 |
| /workspace/coverage/default/12.prim_esc_test.26984476 |
| /workspace/coverage/default/13.prim_esc_test.1679115353 |
| /workspace/coverage/default/14.prim_esc_test.2891332072 |
| /workspace/coverage/default/17.prim_esc_test.815606260 |
| /workspace/coverage/default/18.prim_esc_test.1887706023 |
| /workspace/coverage/default/19.prim_esc_test.3136138592 |
| /workspace/coverage/default/2.prim_esc_test.4265842818 |
| /workspace/coverage/default/3.prim_esc_test.3898695919 |
| /workspace/coverage/default/4.prim_esc_test.985327158 |
| /workspace/coverage/default/5.prim_esc_test.3354256437 |
| /workspace/coverage/default/6.prim_esc_test.3554755302 |
| /workspace/coverage/default/7.prim_esc_test.2442988064 |
| /workspace/coverage/default/8.prim_esc_test.3069087034 |
| /workspace/coverage/default/9.prim_esc_test.3254494462 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/5.prim_esc_test.3354256437 | Jul 14 04:17:09 PM PDT 24 | Jul 14 04:17:11 PM PDT 24 | 4509658 ps | ||
| T2 | /workspace/coverage/default/7.prim_esc_test.2442988064 | Jul 14 04:17:11 PM PDT 24 | Jul 14 04:17:14 PM PDT 24 | 4057033 ps | ||
| T3 | /workspace/coverage/default/3.prim_esc_test.3898695919 | Jul 14 04:21:49 PM PDT 24 | Jul 14 04:21:50 PM PDT 24 | 5330694 ps | ||
| T9 | /workspace/coverage/default/18.prim_esc_test.1887706023 | Jul 14 04:21:45 PM PDT 24 | Jul 14 04:21:47 PM PDT 24 | 4878124 ps | ||
| T12 | /workspace/coverage/default/16.prim_esc_test.136761559 | Jul 14 04:22:05 PM PDT 24 | Jul 14 04:22:07 PM PDT 24 | 4689078 ps | ||
| T4 | /workspace/coverage/default/0.prim_esc_test.2813480425 | Jul 14 04:17:56 PM PDT 24 | Jul 14 04:17:57 PM PDT 24 | 4879180 ps | ||
| T5 | /workspace/coverage/default/1.prim_esc_test.2056394078 | Jul 14 04:17:09 PM PDT 24 | Jul 14 04:17:11 PM PDT 24 | 4934747 ps | ||
| T6 | /workspace/coverage/default/17.prim_esc_test.815606260 | Jul 14 04:22:05 PM PDT 24 | Jul 14 04:22:07 PM PDT 24 | 4652205 ps | ||
| T10 | /workspace/coverage/default/4.prim_esc_test.985327158 | Jul 14 04:17:16 PM PDT 24 | Jul 14 04:17:17 PM PDT 24 | 4314827 ps | ||
| T11 | /workspace/coverage/default/2.prim_esc_test.4265842818 | Jul 14 04:17:09 PM PDT 24 | Jul 14 04:17:11 PM PDT 24 | 4406441 ps | ||
| T7 | /workspace/coverage/default/19.prim_esc_test.3136138592 | Jul 14 04:18:25 PM PDT 24 | Jul 14 04:18:26 PM PDT 24 | 4976886 ps | ||
| T13 | /workspace/coverage/default/15.prim_esc_test.3096445490 | Jul 14 04:21:45 PM PDT 24 | Jul 14 04:21:46 PM PDT 24 | 4501091 ps | ||
| T8 | /workspace/coverage/default/11.prim_esc_test.2607885475 | Jul 14 04:21:59 PM PDT 24 | Jul 14 04:22:01 PM PDT 24 | 5041220 ps | ||
| T15 | /workspace/coverage/default/12.prim_esc_test.26984476 | Jul 14 04:22:05 PM PDT 24 | Jul 14 04:22:07 PM PDT 24 | 4672033 ps | ||
| T16 | /workspace/coverage/default/13.prim_esc_test.1679115353 | Jul 14 04:22:05 PM PDT 24 | Jul 14 04:22:06 PM PDT 24 | 5347089 ps | ||
| T17 | /workspace/coverage/default/14.prim_esc_test.2891332072 | Jul 14 04:18:46 PM PDT 24 | Jul 14 04:18:47 PM PDT 24 | 4988334 ps | ||
| T14 | /workspace/coverage/default/8.prim_esc_test.3069087034 | Jul 14 04:17:10 PM PDT 24 | Jul 14 04:17:13 PM PDT 24 | 4532515 ps | ||
| T18 | /workspace/coverage/default/6.prim_esc_test.3554755302 | Jul 14 04:16:55 PM PDT 24 | Jul 14 04:16:56 PM PDT 24 | 4742576 ps | ||
| T19 | /workspace/coverage/default/10.prim_esc_test.3006504585 | Jul 14 04:21:45 PM PDT 24 | Jul 14 04:21:46 PM PDT 24 | 4299400 ps | ||
| T20 | /workspace/coverage/default/9.prim_esc_test.3254494462 | Jul 14 04:17:08 PM PDT 24 | Jul 14 04:17:09 PM PDT 24 | 5223601 ps |
| Test location | /workspace/coverage/default/1.prim_esc_test.2056394078 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4934747 ps |
| CPU time | 0.48 seconds |
| Started | Jul 14 04:17:09 PM PDT 24 |
| Finished | Jul 14 04:17:11 PM PDT 24 |
| Peak memory | 143844 kb |
| Host | smart-d73034fa-f79c-40c8-9091-cad4bd3add13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056394078 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2056394078 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3096445490 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4501091 ps |
| CPU time | 0.41 seconds |
| Started | Jul 14 04:21:45 PM PDT 24 |
| Finished | Jul 14 04:21:46 PM PDT 24 |
| Peak memory | 146084 kb |
| Host | smart-b097f524-8b00-4741-8098-b2ffa176091a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3096445490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3096445490 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.136761559 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4689078 ps |
| CPU time | 0.39 seconds |
| Started | Jul 14 04:22:05 PM PDT 24 |
| Finished | Jul 14 04:22:07 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-ea2e6e74-99a3-4019-bcc4-ec4835ade28b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=136761559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.136761559 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3006504585 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4299400 ps |
| CPU time | 0.36 seconds |
| Started | Jul 14 04:21:45 PM PDT 24 |
| Finished | Jul 14 04:21:46 PM PDT 24 |
| Peak memory | 145828 kb |
| Host | smart-3f4de2ce-b386-40fb-b307-5f65eed40c9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3006504585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3006504585 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2813480425 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4879180 ps |
| CPU time | 0.39 seconds |
| Started | Jul 14 04:17:56 PM PDT 24 |
| Finished | Jul 14 04:17:57 PM PDT 24 |
| Peak memory | 145996 kb |
| Host | smart-8b1aa832-0e8b-4ed4-87be-eac8dab07eea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2813480425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2813480425 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2607885475 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5041220 ps |
| CPU time | 0.36 seconds |
| Started | Jul 14 04:21:59 PM PDT 24 |
| Finished | Jul 14 04:22:01 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-a4f8beb4-dd19-4d85-8443-edbd68de092a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607885475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2607885475 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.26984476 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4672033 ps |
| CPU time | 0.38 seconds |
| Started | Jul 14 04:22:05 PM PDT 24 |
| Finished | Jul 14 04:22:07 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-b6c1d225-bc8b-45b0-9fcd-8584162a4561 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=26984476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.26984476 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1679115353 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5347089 ps |
| CPU time | 0.38 seconds |
| Started | Jul 14 04:22:05 PM PDT 24 |
| Finished | Jul 14 04:22:06 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-a16b9e33-73ec-49f0-b51b-a505ee426c6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1679115353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1679115353 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2891332072 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4988334 ps |
| CPU time | 0.38 seconds |
| Started | Jul 14 04:18:46 PM PDT 24 |
| Finished | Jul 14 04:18:47 PM PDT 24 |
| Peak memory | 146040 kb |
| Host | smart-52647140-ec69-405d-9628-ae0a699a3524 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2891332072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2891332072 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.815606260 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4652205 ps |
| CPU time | 0.39 seconds |
| Started | Jul 14 04:22:05 PM PDT 24 |
| Finished | Jul 14 04:22:07 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-8d6c6396-eccf-42a8-b7e1-472b55b32698 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=815606260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.815606260 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1887706023 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4878124 ps |
| CPU time | 0.36 seconds |
| Started | Jul 14 04:21:45 PM PDT 24 |
| Finished | Jul 14 04:21:47 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-eaac168e-2ec3-4818-b514-64573d656554 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1887706023 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1887706023 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3136138592 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4976886 ps |
| CPU time | 0.38 seconds |
| Started | Jul 14 04:18:25 PM PDT 24 |
| Finished | Jul 14 04:18:26 PM PDT 24 |
| Peak memory | 145980 kb |
| Host | smart-132e1197-f68a-44fc-ae3b-ce7f975407cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3136138592 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3136138592 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.4265842818 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4406441 ps |
| CPU time | 0.48 seconds |
| Started | Jul 14 04:17:09 PM PDT 24 |
| Finished | Jul 14 04:17:11 PM PDT 24 |
| Peak memory | 143760 kb |
| Host | smart-2c60b248-30ce-46a6-95c1-f55e1930b88d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4265842818 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.4265842818 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3898695919 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5330694 ps |
| CPU time | 0.38 seconds |
| Started | Jul 14 04:21:49 PM PDT 24 |
| Finished | Jul 14 04:21:50 PM PDT 24 |
| Peak memory | 145492 kb |
| Host | smart-19b94d97-10ac-4600-8d2b-b9e4f93b716e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898695919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3898695919 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.985327158 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4314827 ps |
| CPU time | 0.35 seconds |
| Started | Jul 14 04:17:16 PM PDT 24 |
| Finished | Jul 14 04:17:17 PM PDT 24 |
| Peak memory | 146152 kb |
| Host | smart-d97bc543-3620-458a-a447-e9ddc3a480cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985327158 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.985327158 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3354256437 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4509658 ps |
| CPU time | 0.49 seconds |
| Started | Jul 14 04:17:09 PM PDT 24 |
| Finished | Jul 14 04:17:11 PM PDT 24 |
| Peak memory | 144148 kb |
| Host | smart-9a0d8d78-0004-403e-a853-454eca7f15d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3354256437 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3354256437 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3554755302 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4742576 ps |
| CPU time | 0.45 seconds |
| Started | Jul 14 04:16:55 PM PDT 24 |
| Finished | Jul 14 04:16:56 PM PDT 24 |
| Peak memory | 146372 kb |
| Host | smart-1ebf886c-477d-4d29-a1d6-618f6a44bdc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554755302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3554755302 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.2442988064 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4057033 ps |
| CPU time | 0.38 seconds |
| Started | Jul 14 04:17:11 PM PDT 24 |
| Finished | Jul 14 04:17:14 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-0ed6dee6-c91a-4c42-9202-90dbc46fe9b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2442988064 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2442988064 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3069087034 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4532515 ps |
| CPU time | 0.44 seconds |
| Started | Jul 14 04:17:10 PM PDT 24 |
| Finished | Jul 14 04:17:13 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-7ba139f3-82e4-4ef9-9c3a-a8cbc995113d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069087034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3069087034 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3254494462 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5223601 ps |
| CPU time | 0.36 seconds |
| Started | Jul 14 04:17:08 PM PDT 24 |
| Finished | Jul 14 04:17:09 PM PDT 24 |
| Peak memory | 145960 kb |
| Host | smart-44ff9935-9d42-4a83-addc-b1e3e7e1e04c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3254494462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3254494462 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |