| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.23 | 85.23 | 90.48 | 90.48 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/18.prim_esc_test.1445036761 |
| 88.27 | 3.04 | 93.33 | 2.86 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.1858499089 |
| 89.41 | 1.14 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.397932518 |
| 90.55 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.3860469454 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/11.prim_esc_test.1794693587 |
| Name |
|---|
| /workspace/coverage/default/10.prim_esc_test.1428917297 |
| /workspace/coverage/default/12.prim_esc_test.1210105388 |
| /workspace/coverage/default/14.prim_esc_test.183437713 |
| /workspace/coverage/default/15.prim_esc_test.1348301075 |
| /workspace/coverage/default/16.prim_esc_test.1862061127 |
| /workspace/coverage/default/17.prim_esc_test.3598658812 |
| /workspace/coverage/default/19.prim_esc_test.1453444754 |
| /workspace/coverage/default/2.prim_esc_test.1226140872 |
| /workspace/coverage/default/3.prim_esc_test.156587303 |
| /workspace/coverage/default/4.prim_esc_test.2336356434 |
| /workspace/coverage/default/5.prim_esc_test.4267697767 |
| /workspace/coverage/default/6.prim_esc_test.3491252230 |
| /workspace/coverage/default/7.prim_esc_test.2879382369 |
| /workspace/coverage/default/8.prim_esc_test.3580272006 |
| /workspace/coverage/default/9.prim_esc_test.953165137 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/0.prim_esc_test.397932518 | Jul 15 04:26:11 PM PDT 24 | Jul 15 04:26:12 PM PDT 24 | 4721763 ps | ||
| T2 | /workspace/coverage/default/2.prim_esc_test.1226140872 | Jul 15 04:25:02 PM PDT 24 | Jul 15 04:25:03 PM PDT 24 | 4477634 ps | ||
| T3 | /workspace/coverage/default/18.prim_esc_test.1445036761 | Jul 15 04:27:44 PM PDT 24 | Jul 15 04:27:47 PM PDT 24 | 4568868 ps | ||
| T4 | /workspace/coverage/default/4.prim_esc_test.2336356434 | Jul 15 04:24:37 PM PDT 24 | Jul 15 04:24:38 PM PDT 24 | 5289341 ps | ||
| T11 | /workspace/coverage/default/17.prim_esc_test.3598658812 | Jul 15 04:26:32 PM PDT 24 | Jul 15 04:26:33 PM PDT 24 | 5022646 ps | ||
| T5 | /workspace/coverage/default/19.prim_esc_test.1453444754 | Jul 15 04:23:46 PM PDT 24 | Jul 15 04:23:47 PM PDT 24 | 4942829 ps | ||
| T12 | /workspace/coverage/default/5.prim_esc_test.4267697767 | Jul 15 04:24:27 PM PDT 24 | Jul 15 04:24:28 PM PDT 24 | 4881940 ps | ||
| T6 | /workspace/coverage/default/1.prim_esc_test.3860469454 | Jul 15 04:28:02 PM PDT 24 | Jul 15 04:28:06 PM PDT 24 | 4842661 ps | ||
| T9 | /workspace/coverage/default/3.prim_esc_test.156587303 | Jul 15 04:25:59 PM PDT 24 | Jul 15 04:26:01 PM PDT 24 | 4788509 ps | ||
| T13 | /workspace/coverage/default/16.prim_esc_test.1862061127 | Jul 15 04:26:22 PM PDT 24 | Jul 15 04:26:24 PM PDT 24 | 5079056 ps | ||
| T16 | /workspace/coverage/default/12.prim_esc_test.1210105388 | Jul 15 04:23:39 PM PDT 24 | Jul 15 04:23:40 PM PDT 24 | 4763350 ps | ||
| T7 | /workspace/coverage/default/10.prim_esc_test.1428917297 | Jul 15 04:25:14 PM PDT 24 | Jul 15 04:25:15 PM PDT 24 | 4565635 ps | ||
| T14 | /workspace/coverage/default/15.prim_esc_test.1348301075 | Jul 15 04:27:55 PM PDT 24 | Jul 15 04:28:01 PM PDT 24 | 4533002 ps | ||
| T8 | /workspace/coverage/default/7.prim_esc_test.2879382369 | Jul 15 04:24:24 PM PDT 24 | Jul 15 04:24:25 PM PDT 24 | 4393066 ps | ||
| T17 | /workspace/coverage/default/14.prim_esc_test.183437713 | Jul 15 04:25:57 PM PDT 24 | Jul 15 04:25:59 PM PDT 24 | 4602705 ps | ||
| T18 | /workspace/coverage/default/6.prim_esc_test.3491252230 | Jul 15 04:27:05 PM PDT 24 | Jul 15 04:27:06 PM PDT 24 | 4698060 ps | ||
| T15 | /workspace/coverage/default/11.prim_esc_test.1794693587 | Jul 15 04:25:23 PM PDT 24 | Jul 15 04:25:24 PM PDT 24 | 5072066 ps | ||
| T10 | /workspace/coverage/default/13.prim_esc_test.1858499089 | Jul 15 04:22:32 PM PDT 24 | Jul 15 04:22:33 PM PDT 24 | 4618813 ps | ||
| T19 | /workspace/coverage/default/8.prim_esc_test.3580272006 | Jul 15 04:24:50 PM PDT 24 | Jul 15 04:24:51 PM PDT 24 | 4756616 ps | ||
| T20 | /workspace/coverage/default/9.prim_esc_test.953165137 | Jul 15 04:22:15 PM PDT 24 | Jul 15 04:22:17 PM PDT 24 | 5150658 ps |
| Test location | /workspace/coverage/default/18.prim_esc_test.1445036761 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4568868 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 04:27:44 PM PDT 24 |
| Finished | Jul 15 04:27:47 PM PDT 24 |
| Peak memory | 145980 kb |
| Host | smart-03089551-e846-4885-a045-c4c1d68797c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1445036761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1445036761 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1858499089 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4618813 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 04:22:32 PM PDT 24 |
| Finished | Jul 15 04:22:33 PM PDT 24 |
| Peak memory | 146028 kb |
| Host | smart-2319a327-c3f4-4500-9bf8-89fc711929fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1858499089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1858499089 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.397932518 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4721763 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 04:26:11 PM PDT 24 |
| Finished | Jul 15 04:26:12 PM PDT 24 |
| Peak memory | 145992 kb |
| Host | smart-5fa092c0-1aac-404b-8e14-525e37fdfdaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=397932518 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.397932518 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3860469454 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4842661 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 04:28:02 PM PDT 24 |
| Finished | Jul 15 04:28:06 PM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-96ab5389-40ce-4bb0-9f77-f144b1a8e9b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3860469454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3860469454 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1794693587 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5072066 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 04:25:23 PM PDT 24 |
| Finished | Jul 15 04:25:24 PM PDT 24 |
| Peak memory | 146032 kb |
| Host | smart-9fbb4040-eb5e-4f1f-abc0-340837f2d5a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1794693587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1794693587 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1428917297 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4565635 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 04:25:14 PM PDT 24 |
| Finished | Jul 15 04:25:15 PM PDT 24 |
| Peak memory | 146260 kb |
| Host | smart-22631992-fd89-494e-a7e5-4c6656b3a900 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1428917297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1428917297 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1210105388 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4763350 ps |
| CPU time | 0.41 seconds |
| Started | Jul 15 04:23:39 PM PDT 24 |
| Finished | Jul 15 04:23:40 PM PDT 24 |
| Peak memory | 146080 kb |
| Host | smart-c48a2a90-bd95-49d4-9c45-f11b4c604009 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210105388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1210105388 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.183437713 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4602705 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 04:25:57 PM PDT 24 |
| Finished | Jul 15 04:25:59 PM PDT 24 |
| Peak memory | 146004 kb |
| Host | smart-0f41729a-90d1-41ec-9bc3-336ff895d3ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=183437713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.183437713 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1348301075 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4533002 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 04:27:55 PM PDT 24 |
| Finished | Jul 15 04:28:01 PM PDT 24 |
| Peak memory | 146128 kb |
| Host | smart-a9542755-e35b-4afb-96a4-20ecdc1817ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1348301075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1348301075 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1862061127 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5079056 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 04:26:22 PM PDT 24 |
| Finished | Jul 15 04:26:24 PM PDT 24 |
| Peak memory | 146004 kb |
| Host | smart-2e57f81d-9a94-44cd-bb37-ec80f1b0291a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1862061127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1862061127 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3598658812 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5022646 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 04:26:32 PM PDT 24 |
| Finished | Jul 15 04:26:33 PM PDT 24 |
| Peak memory | 146044 kb |
| Host | smart-6e0aead4-3970-422c-93cf-a3a3f8915edf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598658812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3598658812 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1453444754 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4942829 ps |
| CPU time | 0.4 seconds |
| Started | Jul 15 04:23:46 PM PDT 24 |
| Finished | Jul 15 04:23:47 PM PDT 24 |
| Peak memory | 146272 kb |
| Host | smart-9623d240-5943-4b3e-983a-9533cbc58170 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453444754 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1453444754 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1226140872 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4477634 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 04:25:02 PM PDT 24 |
| Finished | Jul 15 04:25:03 PM PDT 24 |
| Peak memory | 145940 kb |
| Host | smart-5326784f-44f8-498f-b079-01ef8d89ffc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1226140872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1226140872 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.156587303 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4788509 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 04:25:59 PM PDT 24 |
| Finished | Jul 15 04:26:01 PM PDT 24 |
| Peak memory | 145996 kb |
| Host | smart-8e6eff89-f4fc-4292-a056-4bf24c7c33fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=156587303 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.156587303 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2336356434 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5289341 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 04:24:37 PM PDT 24 |
| Finished | Jul 15 04:24:38 PM PDT 24 |
| Peak memory | 145928 kb |
| Host | smart-95b34b43-2bf6-4040-a8de-2cfd14f1e34a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336356434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2336356434 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.4267697767 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4881940 ps |
| CPU time | 0.37 seconds |
| Started | Jul 15 04:24:27 PM PDT 24 |
| Finished | Jul 15 04:24:28 PM PDT 24 |
| Peak memory | 145924 kb |
| Host | smart-6bef2e14-158b-407b-9deb-5da1a791151c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4267697767 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.4267697767 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3491252230 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4698060 ps |
| CPU time | 0.38 seconds |
| Started | Jul 15 04:27:05 PM PDT 24 |
| Finished | Jul 15 04:27:06 PM PDT 24 |
| Peak memory | 146020 kb |
| Host | smart-f6ed5dd1-19ba-4999-8706-cffad080d318 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3491252230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3491252230 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.2879382369 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4393066 ps |
| CPU time | 0.39 seconds |
| Started | Jul 15 04:24:24 PM PDT 24 |
| Finished | Jul 15 04:24:25 PM PDT 24 |
| Peak memory | 146272 kb |
| Host | smart-76b36f90-bbf9-43d8-a5a2-81aa56ae2ea3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2879382369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2879382369 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3580272006 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4756616 ps |
| CPU time | 0.36 seconds |
| Started | Jul 15 04:24:50 PM PDT 24 |
| Finished | Jul 15 04:24:51 PM PDT 24 |
| Peak memory | 145844 kb |
| Host | smart-56cd8e78-4ea6-4f12-ad8b-7e74b73a70b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3580272006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3580272006 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.953165137 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5150658 ps |
| CPU time | 0.41 seconds |
| Started | Jul 15 04:22:15 PM PDT 24 |
| Finished | Jul 15 04:22:17 PM PDT 24 |
| Peak memory | 145992 kb |
| Host | smart-cf8d9f45-398c-4e30-b737-b6e3a07df2cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=953165137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.953165137 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |