| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 90.01 | 94.29 | 85.37 | 100.00 | 92.86 | 86.05 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.23 | 85.23 | 90.48 | 90.48 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/1.prim_esc_test.3615709058 |
| 88.27 | 3.04 | 93.33 | 2.86 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.1380824682 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.1272351795 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.329980981 |
| /workspace/coverage/default/11.prim_esc_test.1823615673 |
| /workspace/coverage/default/12.prim_esc_test.2165073945 |
| /workspace/coverage/default/13.prim_esc_test.4021515796 |
| /workspace/coverage/default/15.prim_esc_test.3443781523 |
| /workspace/coverage/default/16.prim_esc_test.3638668966 |
| /workspace/coverage/default/17.prim_esc_test.1825736773 |
| /workspace/coverage/default/18.prim_esc_test.41014710 |
| /workspace/coverage/default/19.prim_esc_test.3956087179 |
| /workspace/coverage/default/2.prim_esc_test.1781554695 |
| /workspace/coverage/default/3.prim_esc_test.27295949 |
| /workspace/coverage/default/4.prim_esc_test.3197027153 |
| /workspace/coverage/default/5.prim_esc_test.3582557010 |
| /workspace/coverage/default/6.prim_esc_test.22441787 |
| /workspace/coverage/default/7.prim_esc_test.144807058 |
| /workspace/coverage/default/8.prim_esc_test.545517911 |
| /workspace/coverage/default/9.prim_esc_test.3787034438 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/2.prim_esc_test.1781554695 | Jul 16 04:35:45 PM PDT 24 | Jul 16 04:35:46 PM PDT 24 | 4562010 ps | ||
| T2 | /workspace/coverage/default/1.prim_esc_test.3615709058 | Jul 16 04:39:43 PM PDT 24 | Jul 16 04:39:44 PM PDT 24 | 4829679 ps | ||
| T3 | /workspace/coverage/default/0.prim_esc_test.329980981 | Jul 16 04:37:03 PM PDT 24 | Jul 16 04:37:04 PM PDT 24 | 4128535 ps | ||
| T5 | /workspace/coverage/default/14.prim_esc_test.1272351795 | Jul 16 04:34:37 PM PDT 24 | Jul 16 04:34:37 PM PDT 24 | 5156395 ps | ||
| T4 | /workspace/coverage/default/7.prim_esc_test.144807058 | Jul 16 04:35:33 PM PDT 24 | Jul 16 04:35:34 PM PDT 24 | 4725824 ps | ||
| T12 | /workspace/coverage/default/19.prim_esc_test.3956087179 | Jul 16 04:35:27 PM PDT 24 | Jul 16 04:35:28 PM PDT 24 | 4946077 ps | ||
| T7 | /workspace/coverage/default/12.prim_esc_test.2165073945 | Jul 16 04:34:24 PM PDT 24 | Jul 16 04:34:25 PM PDT 24 | 4343186 ps | ||
| T8 | /workspace/coverage/default/10.prim_esc_test.1380824682 | Jul 16 04:35:33 PM PDT 24 | Jul 16 04:35:34 PM PDT 24 | 5094909 ps | ||
| T11 | /workspace/coverage/default/5.prim_esc_test.3582557010 | Jul 16 04:35:37 PM PDT 24 | Jul 16 04:35:38 PM PDT 24 | 5308982 ps | ||
| T6 | /workspace/coverage/default/3.prim_esc_test.27295949 | Jul 16 04:37:16 PM PDT 24 | Jul 16 04:37:17 PM PDT 24 | 4730799 ps | ||
| T9 | /workspace/coverage/default/13.prim_esc_test.4021515796 | Jul 16 04:35:37 PM PDT 24 | Jul 16 04:35:38 PM PDT 24 | 5010054 ps | ||
| T10 | /workspace/coverage/default/18.prim_esc_test.41014710 | Jul 16 04:40:10 PM PDT 24 | Jul 16 04:40:12 PM PDT 24 | 5341309 ps | ||
| T13 | /workspace/coverage/default/16.prim_esc_test.3638668966 | Jul 16 04:34:30 PM PDT 24 | Jul 16 04:34:31 PM PDT 24 | 4733714 ps | ||
| T14 | /workspace/coverage/default/8.prim_esc_test.545517911 | Jul 16 04:35:55 PM PDT 24 | Jul 16 04:35:56 PM PDT 24 | 4575763 ps | ||
| T15 | /workspace/coverage/default/9.prim_esc_test.3787034438 | Jul 16 04:34:37 PM PDT 24 | Jul 16 04:34:38 PM PDT 24 | 4734993 ps | ||
| T16 | /workspace/coverage/default/4.prim_esc_test.3197027153 | Jul 16 04:35:33 PM PDT 24 | Jul 16 04:35:34 PM PDT 24 | 5258528 ps | ||
| T17 | /workspace/coverage/default/17.prim_esc_test.1825736773 | Jul 16 04:35:41 PM PDT 24 | Jul 16 04:35:42 PM PDT 24 | 4648009 ps | ||
| T18 | /workspace/coverage/default/11.prim_esc_test.1823615673 | Jul 16 04:34:34 PM PDT 24 | Jul 16 04:34:36 PM PDT 24 | 4648894 ps | ||
| T19 | /workspace/coverage/default/15.prim_esc_test.3443781523 | Jul 16 04:35:40 PM PDT 24 | Jul 16 04:35:42 PM PDT 24 | 5429167 ps | ||
| T20 | /workspace/coverage/default/6.prim_esc_test.22441787 | Jul 16 04:35:52 PM PDT 24 | Jul 16 04:35:53 PM PDT 24 | 5084274 ps |
| Test location | /workspace/coverage/default/1.prim_esc_test.3615709058 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4829679 ps |
| CPU time | 0.37 seconds |
| Started | Jul 16 04:39:43 PM PDT 24 |
| Finished | Jul 16 04:39:44 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-234fd013-4235-4b15-86de-83f0f3441d2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3615709058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3615709058 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1380824682 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5094909 ps |
| CPU time | 0.4 seconds |
| Started | Jul 16 04:35:33 PM PDT 24 |
| Finished | Jul 16 04:35:34 PM PDT 24 |
| Peak memory | 145268 kb |
| Host | smart-5a2feb0d-1eb8-4ad9-8a3c-72dddb1eb70b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1380824682 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1380824682 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1272351795 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5156395 ps |
| CPU time | 0.38 seconds |
| Started | Jul 16 04:34:37 PM PDT 24 |
| Finished | Jul 16 04:34:37 PM PDT 24 |
| Peak memory | 145684 kb |
| Host | smart-49245eec-cd55-4b8b-8acf-66bfa7a1c2ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1272351795 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1272351795 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.329980981 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4128535 ps |
| CPU time | 0.4 seconds |
| Started | Jul 16 04:37:03 PM PDT 24 |
| Finished | Jul 16 04:37:04 PM PDT 24 |
| Peak memory | 146044 kb |
| Host | smart-6a0368ab-ffb2-4bb1-89d7-61613adbb139 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329980981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.329980981 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1823615673 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4648894 ps |
| CPU time | 0.39 seconds |
| Started | Jul 16 04:34:34 PM PDT 24 |
| Finished | Jul 16 04:34:36 PM PDT 24 |
| Peak memory | 146260 kb |
| Host | smart-0ef49fa8-db49-4773-893e-c639752a4702 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1823615673 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1823615673 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2165073945 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4343186 ps |
| CPU time | 0.47 seconds |
| Started | Jul 16 04:34:24 PM PDT 24 |
| Finished | Jul 16 04:34:25 PM PDT 24 |
| Peak memory | 146388 kb |
| Host | smart-682b0fc9-6641-4e66-a271-8b518189af37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2165073945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2165073945 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.4021515796 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5010054 ps |
| CPU time | 0.41 seconds |
| Started | Jul 16 04:35:37 PM PDT 24 |
| Finished | Jul 16 04:35:38 PM PDT 24 |
| Peak memory | 144240 kb |
| Host | smart-776c1032-0f80-4b5b-a4d9-6ba37608b13b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4021515796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4021515796 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3443781523 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5429167 ps |
| CPU time | 0.4 seconds |
| Started | Jul 16 04:35:40 PM PDT 24 |
| Finished | Jul 16 04:35:42 PM PDT 24 |
| Peak memory | 146332 kb |
| Host | smart-bd9d9b48-6592-4d84-b3a7-743bc2bb7285 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3443781523 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3443781523 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3638668966 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4733714 ps |
| CPU time | 0.49 seconds |
| Started | Jul 16 04:34:30 PM PDT 24 |
| Finished | Jul 16 04:34:31 PM PDT 24 |
| Peak memory | 146416 kb |
| Host | smart-f09d8705-73b8-46b4-93b9-4bb3be2a5218 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638668966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3638668966 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1825736773 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4648009 ps |
| CPU time | 0.36 seconds |
| Started | Jul 16 04:35:41 PM PDT 24 |
| Finished | Jul 16 04:35:42 PM PDT 24 |
| Peak memory | 146804 kb |
| Host | smart-cb764e1c-2156-440e-9633-8ff8bcfdd5ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1825736773 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1825736773 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.41014710 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5341309 ps |
| CPU time | 0.36 seconds |
| Started | Jul 16 04:40:10 PM PDT 24 |
| Finished | Jul 16 04:40:12 PM PDT 24 |
| Peak memory | 145840 kb |
| Host | smart-a3fcfcf3-d626-40e2-ba04-2c4a14ceda29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=41014710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.41014710 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3956087179 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4946077 ps |
| CPU time | 0.38 seconds |
| Started | Jul 16 04:35:27 PM PDT 24 |
| Finished | Jul 16 04:35:28 PM PDT 24 |
| Peak memory | 146260 kb |
| Host | smart-a024cac3-0f16-4a09-b202-f99bb4aaec96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3956087179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3956087179 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1781554695 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4562010 ps |
| CPU time | 0.38 seconds |
| Started | Jul 16 04:35:45 PM PDT 24 |
| Finished | Jul 16 04:35:46 PM PDT 24 |
| Peak memory | 146000 kb |
| Host | smart-d510c070-c97f-4f82-bffc-622545ee4c41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1781554695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1781554695 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.27295949 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4730799 ps |
| CPU time | 0.37 seconds |
| Started | Jul 16 04:37:16 PM PDT 24 |
| Finished | Jul 16 04:37:17 PM PDT 24 |
| Peak memory | 145996 kb |
| Host | smart-32fe1a21-c358-4778-abe2-fba4f1e03b2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27295949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.27295949 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3197027153 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5258528 ps |
| CPU time | 0.43 seconds |
| Started | Jul 16 04:35:33 PM PDT 24 |
| Finished | Jul 16 04:35:34 PM PDT 24 |
| Peak memory | 145772 kb |
| Host | smart-631582f0-a179-4e97-8f97-368a97620b91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3197027153 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3197027153 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3582557010 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5308982 ps |
| CPU time | 0.42 seconds |
| Started | Jul 16 04:35:37 PM PDT 24 |
| Finished | Jul 16 04:35:38 PM PDT 24 |
| Peak memory | 144228 kb |
| Host | smart-dae76315-40d7-4384-ac92-37141630836a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3582557010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3582557010 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.22441787 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5084274 ps |
| CPU time | 0.38 seconds |
| Started | Jul 16 04:35:52 PM PDT 24 |
| Finished | Jul 16 04:35:53 PM PDT 24 |
| Peak memory | 145720 kb |
| Host | smart-e23d1a2f-f654-47b8-9cd8-ee38d1cbd7e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=22441787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.22441787 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.144807058 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4725824 ps |
| CPU time | 0.36 seconds |
| Started | Jul 16 04:35:33 PM PDT 24 |
| Finished | Jul 16 04:35:34 PM PDT 24 |
| Peak memory | 146512 kb |
| Host | smart-2be2ce5e-27b2-4318-b741-3910d2ff1479 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=144807058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.144807058 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.545517911 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4575763 ps |
| CPU time | 0.39 seconds |
| Started | Jul 16 04:35:55 PM PDT 24 |
| Finished | Jul 16 04:35:56 PM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-460ef2d1-2187-4763-840b-f1257889174a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=545517911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.545517911 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3787034438 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4734993 ps |
| CPU time | 0.4 seconds |
| Started | Jul 16 04:34:37 PM PDT 24 |
| Finished | Jul 16 04:34:38 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-bd3ba5bf-7b82-4246-a550-50a2ccad076c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3787034438 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3787034438 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |