| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.23 | 85.23 | 90.48 | 90.48 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/11.prim_esc_test.1818480189 |
| 88.27 | 3.04 | 93.33 | 2.86 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.3024117465 |
| 90.01 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/17.prim_esc_test.854836107 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.3779370369 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.3763134467 |
| /workspace/coverage/default/1.prim_esc_test.2516495793 |
| /workspace/coverage/default/10.prim_esc_test.275251603 |
| /workspace/coverage/default/12.prim_esc_test.3498452432 |
| /workspace/coverage/default/15.prim_esc_test.407085296 |
| /workspace/coverage/default/16.prim_esc_test.3383424639 |
| /workspace/coverage/default/18.prim_esc_test.324211142 |
| /workspace/coverage/default/19.prim_esc_test.3192026210 |
| /workspace/coverage/default/2.prim_esc_test.322769576 |
| /workspace/coverage/default/3.prim_esc_test.3357848281 |
| /workspace/coverage/default/4.prim_esc_test.1045169499 |
| /workspace/coverage/default/5.prim_esc_test.167480876 |
| /workspace/coverage/default/6.prim_esc_test.336064790 |
| /workspace/coverage/default/7.prim_esc_test.1321368108 |
| /workspace/coverage/default/8.prim_esc_test.1108189418 |
| /workspace/coverage/default/9.prim_esc_test.3861782704 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/8.prim_esc_test.1108189418 | Jul 17 04:19:05 PM PDT 24 | Jul 17 04:19:06 PM PDT 24 | 4171346 ps | ||
| T2 | /workspace/coverage/default/1.prim_esc_test.2516495793 | Jul 17 04:19:16 PM PDT 24 | Jul 17 04:19:17 PM PDT 24 | 4943430 ps | ||
| T3 | /workspace/coverage/default/19.prim_esc_test.3192026210 | Jul 17 04:22:27 PM PDT 24 | Jul 17 04:22:28 PM PDT 24 | 5088953 ps | ||
| T4 | /workspace/coverage/default/15.prim_esc_test.407085296 | Jul 17 04:22:12 PM PDT 24 | Jul 17 04:22:14 PM PDT 24 | 4744256 ps | ||
| T7 | /workspace/coverage/default/6.prim_esc_test.336064790 | Jul 17 04:22:27 PM PDT 24 | Jul 17 04:22:28 PM PDT 24 | 4838098 ps | ||
| T11 | /workspace/coverage/default/14.prim_esc_test.3779370369 | Jul 17 04:20:36 PM PDT 24 | Jul 17 04:20:38 PM PDT 24 | 5007414 ps | ||
| T5 | /workspace/coverage/default/16.prim_esc_test.3383424639 | Jul 17 04:24:27 PM PDT 24 | Jul 17 04:24:29 PM PDT 24 | 4949223 ps | ||
| T6 | /workspace/coverage/default/18.prim_esc_test.324211142 | Jul 17 04:24:30 PM PDT 24 | Jul 17 04:24:33 PM PDT 24 | 4310838 ps | ||
| T8 | /workspace/coverage/default/11.prim_esc_test.1818480189 | Jul 17 04:19:56 PM PDT 24 | Jul 17 04:19:57 PM PDT 24 | 4799488 ps | ||
| T14 | /workspace/coverage/default/10.prim_esc_test.275251603 | Jul 17 04:25:14 PM PDT 24 | Jul 17 04:25:16 PM PDT 24 | 4568830 ps | ||
| T15 | /workspace/coverage/default/7.prim_esc_test.1321368108 | Jul 17 04:19:12 PM PDT 24 | Jul 17 04:19:13 PM PDT 24 | 5029520 ps | ||
| T13 | /workspace/coverage/default/9.prim_esc_test.3861782704 | Jul 17 04:23:08 PM PDT 24 | Jul 17 04:23:10 PM PDT 24 | 4791398 ps | ||
| T16 | /workspace/coverage/default/5.prim_esc_test.167480876 | Jul 17 04:24:30 PM PDT 24 | Jul 17 04:24:32 PM PDT 24 | 4737223 ps | ||
| T17 | /workspace/coverage/default/2.prim_esc_test.322769576 | Jul 17 04:19:55 PM PDT 24 | Jul 17 04:19:57 PM PDT 24 | 4402948 ps | ||
| T18 | /workspace/coverage/default/3.prim_esc_test.3357848281 | Jul 17 04:22:42 PM PDT 24 | Jul 17 04:22:43 PM PDT 24 | 4876821 ps | ||
| T19 | /workspace/coverage/default/0.prim_esc_test.3763134467 | Jul 17 04:24:42 PM PDT 24 | Jul 17 04:24:43 PM PDT 24 | 4607181 ps | ||
| T9 | /workspace/coverage/default/13.prim_esc_test.3024117465 | Jul 17 04:19:54 PM PDT 24 | Jul 17 04:19:55 PM PDT 24 | 4962641 ps | ||
| T10 | /workspace/coverage/default/12.prim_esc_test.3498452432 | Jul 17 04:24:27 PM PDT 24 | Jul 17 04:24:29 PM PDT 24 | 4791172 ps | ||
| T20 | /workspace/coverage/default/4.prim_esc_test.1045169499 | Jul 17 04:19:05 PM PDT 24 | Jul 17 04:19:06 PM PDT 24 | 5139834 ps | ||
| T12 | /workspace/coverage/default/17.prim_esc_test.854836107 | Jul 17 04:22:28 PM PDT 24 | Jul 17 04:22:29 PM PDT 24 | 4929906 ps |
| Test location | /workspace/coverage/default/11.prim_esc_test.1818480189 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4799488 ps |
| CPU time | 0.38 seconds |
| Started | Jul 17 04:19:56 PM PDT 24 |
| Finished | Jul 17 04:19:57 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-8be90184-b6fa-470a-a381-212a68907457 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818480189 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1818480189 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3024117465 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4962641 ps |
| CPU time | 0.39 seconds |
| Started | Jul 17 04:19:54 PM PDT 24 |
| Finished | Jul 17 04:19:55 PM PDT 24 |
| Peak memory | 145812 kb |
| Host | smart-53502c59-b587-48d6-ad19-98f957cf4e81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3024117465 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3024117465 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.854836107 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4929906 ps |
| CPU time | 0.38 seconds |
| Started | Jul 17 04:22:28 PM PDT 24 |
| Finished | Jul 17 04:22:29 PM PDT 24 |
| Peak memory | 145712 kb |
| Host | smart-0a73f4ce-9926-4cc2-a943-d580752bdd23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854836107 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.854836107 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3779370369 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5007414 ps |
| CPU time | 0.41 seconds |
| Started | Jul 17 04:20:36 PM PDT 24 |
| Finished | Jul 17 04:20:38 PM PDT 24 |
| Peak memory | 146244 kb |
| Host | smart-ebd66c9c-ac77-497d-8872-ca06690c1950 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3779370369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3779370369 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3763134467 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4607181 ps |
| CPU time | 0.37 seconds |
| Started | Jul 17 04:24:42 PM PDT 24 |
| Finished | Jul 17 04:24:43 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-5d5bc8d7-2f6d-4caa-b92c-28295c5b1c7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3763134467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3763134467 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2516495793 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4943430 ps |
| CPU time | 0.39 seconds |
| Started | Jul 17 04:19:16 PM PDT 24 |
| Finished | Jul 17 04:19:17 PM PDT 24 |
| Peak memory | 146284 kb |
| Host | smart-0eface22-ed19-4a8b-8c91-d4e149a2cff2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2516495793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2516495793 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.275251603 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4568830 ps |
| CPU time | 0.4 seconds |
| Started | Jul 17 04:25:14 PM PDT 24 |
| Finished | Jul 17 04:25:16 PM PDT 24 |
| Peak memory | 146376 kb |
| Host | smart-af234d55-631c-4ced-92e6-ad38334f561e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=275251603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.275251603 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3498452432 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4791172 ps |
| CPU time | 0.46 seconds |
| Started | Jul 17 04:24:27 PM PDT 24 |
| Finished | Jul 17 04:24:29 PM PDT 24 |
| Peak memory | 144764 kb |
| Host | smart-80ec05cf-696e-4dd9-8d76-c329ebd4388d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3498452432 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3498452432 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.407085296 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4744256 ps |
| CPU time | 0.4 seconds |
| Started | Jul 17 04:22:12 PM PDT 24 |
| Finished | Jul 17 04:22:14 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-551e6ebb-73f8-4492-b97a-32de293b9c95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=407085296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.407085296 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3383424639 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4949223 ps |
| CPU time | 0.45 seconds |
| Started | Jul 17 04:24:27 PM PDT 24 |
| Finished | Jul 17 04:24:29 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-a22648a2-26ba-4f1b-b8ec-ba2bb220ecbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383424639 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3383424639 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.324211142 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4310838 ps |
| CPU time | 0.38 seconds |
| Started | Jul 17 04:24:30 PM PDT 24 |
| Finished | Jul 17 04:24:33 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-e0d14a53-855a-4672-b856-09e3911b3b52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=324211142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.324211142 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3192026210 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5088953 ps |
| CPU time | 0.36 seconds |
| Started | Jul 17 04:22:27 PM PDT 24 |
| Finished | Jul 17 04:22:28 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-e0f4da68-e1be-4824-bcb3-f07bba4e1d1d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3192026210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3192026210 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.322769576 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4402948 ps |
| CPU time | 0.4 seconds |
| Started | Jul 17 04:19:55 PM PDT 24 |
| Finished | Jul 17 04:19:57 PM PDT 24 |
| Peak memory | 146292 kb |
| Host | smart-20ad520b-ded2-4780-af6a-fe397886998b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322769576 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.322769576 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3357848281 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4876821 ps |
| CPU time | 0.37 seconds |
| Started | Jul 17 04:22:42 PM PDT 24 |
| Finished | Jul 17 04:22:43 PM PDT 24 |
| Peak memory | 145756 kb |
| Host | smart-2a799386-c23c-43c3-adf3-b33c4b79dcb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3357848281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3357848281 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1045169499 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5139834 ps |
| CPU time | 0.38 seconds |
| Started | Jul 17 04:19:05 PM PDT 24 |
| Finished | Jul 17 04:19:06 PM PDT 24 |
| Peak memory | 145832 kb |
| Host | smart-54621a12-2ef8-458a-b929-42add5c1b612 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1045169499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1045169499 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.167480876 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4737223 ps |
| CPU time | 0.41 seconds |
| Started | Jul 17 04:24:30 PM PDT 24 |
| Finished | Jul 17 04:24:32 PM PDT 24 |
| Peak memory | 145132 kb |
| Host | smart-d76303fe-c668-4d44-a0fe-108c55e379e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167480876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.167480876 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.336064790 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4838098 ps |
| CPU time | 0.4 seconds |
| Started | Jul 17 04:22:27 PM PDT 24 |
| Finished | Jul 17 04:22:28 PM PDT 24 |
| Peak memory | 145740 kb |
| Host | smart-ff2bc5a2-78a7-4bb1-8de2-caeb53498e5c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=336064790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.336064790 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1321368108 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5029520 ps |
| CPU time | 0.37 seconds |
| Started | Jul 17 04:19:12 PM PDT 24 |
| Finished | Jul 17 04:19:13 PM PDT 24 |
| Peak memory | 146248 kb |
| Host | smart-24a59c5c-5c7b-432e-8abe-f0557327f715 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1321368108 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1321368108 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1108189418 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4171346 ps |
| CPU time | 0.38 seconds |
| Started | Jul 17 04:19:05 PM PDT 24 |
| Finished | Jul 17 04:19:06 PM PDT 24 |
| Peak memory | 145832 kb |
| Host | smart-2dbe0231-887f-400d-a591-e99c664aee8a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108189418 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1108189418 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3861782704 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4791398 ps |
| CPU time | 0.43 seconds |
| Started | Jul 17 04:23:08 PM PDT 24 |
| Finished | Jul 17 04:23:10 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-1ca3d0e3-b04b-426b-861c-c61cb9065a2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861782704 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3861782704 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |