| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.23 | 85.23 | 90.48 | 90.48 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/17.prim_esc_test.825461539 |
| 88.86 | 3.63 | 93.33 | 2.86 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 14.29 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.2761187787 |
| 90.01 | 1.14 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/19.prim_esc_test.3431840898 |
| 91.15 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/6.prim_esc_test.3524962336 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2174691197 |
| /workspace/coverage/default/1.prim_esc_test.478410700 |
| /workspace/coverage/default/10.prim_esc_test.1795427638 |
| /workspace/coverage/default/11.prim_esc_test.3495145520 |
| /workspace/coverage/default/12.prim_esc_test.3412645496 |
| /workspace/coverage/default/13.prim_esc_test.3827354882 |
| /workspace/coverage/default/15.prim_esc_test.10298996 |
| /workspace/coverage/default/16.prim_esc_test.1460181063 |
| /workspace/coverage/default/18.prim_esc_test.266382973 |
| /workspace/coverage/default/2.prim_esc_test.1643167816 |
| /workspace/coverage/default/3.prim_esc_test.2782331990 |
| /workspace/coverage/default/4.prim_esc_test.903710765 |
| /workspace/coverage/default/5.prim_esc_test.4105711388 |
| /workspace/coverage/default/7.prim_esc_test.3399307463 |
| /workspace/coverage/default/8.prim_esc_test.335737508 |
| /workspace/coverage/default/9.prim_esc_test.315608942 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/11.prim_esc_test.3495145520 | Jul 18 04:30:50 PM PDT 24 | Jul 18 04:30:51 PM PDT 24 | 4350778 ps | ||
| T2 | /workspace/coverage/default/15.prim_esc_test.10298996 | Jul 18 04:35:49 PM PDT 24 | Jul 18 04:35:50 PM PDT 24 | 4554019 ps | ||
| T3 | /workspace/coverage/default/6.prim_esc_test.3524962336 | Jul 18 04:30:12 PM PDT 24 | Jul 18 04:30:14 PM PDT 24 | 5120925 ps | ||
| T12 | /workspace/coverage/default/8.prim_esc_test.335737508 | Jul 18 04:30:13 PM PDT 24 | Jul 18 04:30:15 PM PDT 24 | 4971383 ps | ||
| T14 | /workspace/coverage/default/1.prim_esc_test.478410700 | Jul 18 04:30:10 PM PDT 24 | Jul 18 04:30:11 PM PDT 24 | 5107476 ps | ||
| T4 | /workspace/coverage/default/17.prim_esc_test.825461539 | Jul 18 04:35:46 PM PDT 24 | Jul 18 04:35:47 PM PDT 24 | 5460758 ps | ||
| T5 | /workspace/coverage/default/10.prim_esc_test.1795427638 | Jul 18 04:30:09 PM PDT 24 | Jul 18 04:30:11 PM PDT 24 | 4921095 ps | ||
| T11 | /workspace/coverage/default/3.prim_esc_test.2782331990 | Jul 18 04:30:09 PM PDT 24 | Jul 18 04:30:11 PM PDT 24 | 4439631 ps | ||
| T6 | /workspace/coverage/default/0.prim_esc_test.2174691197 | Jul 18 04:30:10 PM PDT 24 | Jul 18 04:30:11 PM PDT 24 | 5055096 ps | ||
| T10 | /workspace/coverage/default/2.prim_esc_test.1643167816 | Jul 18 04:30:11 PM PDT 24 | Jul 18 04:30:13 PM PDT 24 | 5317645 ps | ||
| T15 | /workspace/coverage/default/9.prim_esc_test.315608942 | Jul 18 04:30:10 PM PDT 24 | Jul 18 04:30:12 PM PDT 24 | 5382507 ps | ||
| T16 | /workspace/coverage/default/12.prim_esc_test.3412645496 | Jul 18 04:30:25 PM PDT 24 | Jul 18 04:30:26 PM PDT 24 | 4716077 ps | ||
| T7 | /workspace/coverage/default/14.prim_esc_test.2761187787 | Jul 18 04:35:56 PM PDT 24 | Jul 18 04:35:57 PM PDT 24 | 4944704 ps | ||
| T8 | /workspace/coverage/default/13.prim_esc_test.3827354882 | Jul 18 04:30:14 PM PDT 24 | Jul 18 04:30:15 PM PDT 24 | 5157072 ps | ||
| T17 | /workspace/coverage/default/7.prim_esc_test.3399307463 | Jul 18 04:30:12 PM PDT 24 | Jul 18 04:30:14 PM PDT 24 | 4850634 ps | ||
| T18 | /workspace/coverage/default/16.prim_esc_test.1460181063 | Jul 18 04:35:55 PM PDT 24 | Jul 18 04:35:56 PM PDT 24 | 4683556 ps | ||
| T19 | /workspace/coverage/default/18.prim_esc_test.266382973 | Jul 18 04:35:50 PM PDT 24 | Jul 18 04:35:51 PM PDT 24 | 5052976 ps | ||
| T13 | /workspace/coverage/default/19.prim_esc_test.3431840898 | Jul 18 04:37:03 PM PDT 24 | Jul 18 04:37:04 PM PDT 24 | 5437078 ps | ||
| T20 | /workspace/coverage/default/5.prim_esc_test.4105711388 | Jul 18 04:30:06 PM PDT 24 | Jul 18 04:30:08 PM PDT 24 | 4198400 ps | ||
| T9 | /workspace/coverage/default/4.prim_esc_test.903710765 | Jul 18 04:30:12 PM PDT 24 | Jul 18 04:30:13 PM PDT 24 | 4923972 ps |
| Test location | /workspace/coverage/default/17.prim_esc_test.825461539 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5460758 ps |
| CPU time | 0.38 seconds |
| Started | Jul 18 04:35:46 PM PDT 24 |
| Finished | Jul 18 04:35:47 PM PDT 24 |
| Peak memory | 145708 kb |
| Host | smart-27c92192-a5f8-4038-8353-05350339094f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=825461539 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.825461539 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2761187787 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4944704 ps |
| CPU time | 0.39 seconds |
| Started | Jul 18 04:35:56 PM PDT 24 |
| Finished | Jul 18 04:35:57 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-3fbbaf0e-a063-46fe-8874-3dd808e9168f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2761187787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2761187787 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3431840898 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5437078 ps |
| CPU time | 0.4 seconds |
| Started | Jul 18 04:37:03 PM PDT 24 |
| Finished | Jul 18 04:37:04 PM PDT 24 |
| Peak memory | 145336 kb |
| Host | smart-740218e6-f08a-4f0c-86cf-33c00fa802f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3431840898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3431840898 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3524962336 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5120925 ps |
| CPU time | 0.39 seconds |
| Started | Jul 18 04:30:12 PM PDT 24 |
| Finished | Jul 18 04:30:14 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-87a7ede7-ca3a-4a52-8121-9284244c06cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524962336 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3524962336 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2174691197 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5055096 ps |
| CPU time | 0.36 seconds |
| Started | Jul 18 04:30:10 PM PDT 24 |
| Finished | Jul 18 04:30:11 PM PDT 24 |
| Peak memory | 145480 kb |
| Host | smart-7e0c4110-48cf-4fa1-8422-74d27206f37a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174691197 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2174691197 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.478410700 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5107476 ps |
| CPU time | 0.37 seconds |
| Started | Jul 18 04:30:10 PM PDT 24 |
| Finished | Jul 18 04:30:11 PM PDT 24 |
| Peak memory | 146788 kb |
| Host | smart-ab474969-3e17-4f69-b9a5-871d10dcbd20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=478410700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.478410700 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1795427638 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4921095 ps |
| CPU time | 0.41 seconds |
| Started | Jul 18 04:30:09 PM PDT 24 |
| Finished | Jul 18 04:30:11 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-4fe4ad82-2e27-419b-b287-425598606a32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1795427638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1795427638 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3495145520 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4350778 ps |
| CPU time | 0.38 seconds |
| Started | Jul 18 04:30:50 PM PDT 24 |
| Finished | Jul 18 04:30:51 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-63c2adf9-0d19-47c6-9e5e-519d234abb6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3495145520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3495145520 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3412645496 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4716077 ps |
| CPU time | 0.4 seconds |
| Started | Jul 18 04:30:25 PM PDT 24 |
| Finished | Jul 18 04:30:26 PM PDT 24 |
| Peak memory | 145696 kb |
| Host | smart-d2a8cd63-5593-4675-94e6-eddffcaaf235 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412645496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3412645496 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3827354882 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5157072 ps |
| CPU time | 0.42 seconds |
| Started | Jul 18 04:30:14 PM PDT 24 |
| Finished | Jul 18 04:30:15 PM PDT 24 |
| Peak memory | 146376 kb |
| Host | smart-ce36b118-0295-49e5-920a-cfb750ede77c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3827354882 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3827354882 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.10298996 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4554019 ps |
| CPU time | 0.43 seconds |
| Started | Jul 18 04:35:49 PM PDT 24 |
| Finished | Jul 18 04:35:50 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-3dd99d97-5dff-4f44-942e-71b0c314a66a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10298996 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.10298996 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1460181063 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4683556 ps |
| CPU time | 0.38 seconds |
| Started | Jul 18 04:35:55 PM PDT 24 |
| Finished | Jul 18 04:35:56 PM PDT 24 |
| Peak memory | 145768 kb |
| Host | smart-195669b7-5d88-4805-926d-6857e4d9bb84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1460181063 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1460181063 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.266382973 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5052976 ps |
| CPU time | 0.39 seconds |
| Started | Jul 18 04:35:50 PM PDT 24 |
| Finished | Jul 18 04:35:51 PM PDT 24 |
| Peak memory | 145680 kb |
| Host | smart-9357d5f9-c8d2-4b64-9205-89145e28b89d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=266382973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.266382973 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1643167816 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5317645 ps |
| CPU time | 0.39 seconds |
| Started | Jul 18 04:30:11 PM PDT 24 |
| Finished | Jul 18 04:30:13 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-1e0f2ffc-5d0a-4cdb-8d4a-a283388a4560 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643167816 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1643167816 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2782331990 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4439631 ps |
| CPU time | 0.42 seconds |
| Started | Jul 18 04:30:09 PM PDT 24 |
| Finished | Jul 18 04:30:11 PM PDT 24 |
| Peak memory | 146788 kb |
| Host | smart-bc42e033-4e0e-447d-b43b-675062455e7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2782331990 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2782331990 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.903710765 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4923972 ps |
| CPU time | 0.42 seconds |
| Started | Jul 18 04:30:12 PM PDT 24 |
| Finished | Jul 18 04:30:13 PM PDT 24 |
| Peak memory | 146300 kb |
| Host | smart-10ce18cb-94c9-48c6-af3e-84839dd030ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=903710765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.903710765 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.4105711388 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4198400 ps |
| CPU time | 0.45 seconds |
| Started | Jul 18 04:30:06 PM PDT 24 |
| Finished | Jul 18 04:30:08 PM PDT 24 |
| Peak memory | 145600 kb |
| Host | smart-87050003-ef55-4ef9-9d7c-cc6709cf98f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4105711388 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.4105711388 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3399307463 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4850634 ps |
| CPU time | 0.42 seconds |
| Started | Jul 18 04:30:12 PM PDT 24 |
| Finished | Jul 18 04:30:14 PM PDT 24 |
| Peak memory | 144620 kb |
| Host | smart-15847a16-17bd-409d-b1e0-e749e2467488 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399307463 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3399307463 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.335737508 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4971383 ps |
| CPU time | 0.37 seconds |
| Started | Jul 18 04:30:13 PM PDT 24 |
| Finished | Jul 18 04:30:15 PM PDT 24 |
| Peak memory | 146276 kb |
| Host | smart-ebcc34c0-86b7-4854-992c-76fb61d99e42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335737508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.335737508 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.315608942 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5382507 ps |
| CPU time | 0.38 seconds |
| Started | Jul 18 04:30:10 PM PDT 24 |
| Finished | Jul 18 04:30:12 PM PDT 24 |
| Peak memory | 146300 kb |
| Host | smart-f6127292-1e8a-406d-8acd-b5809d19f19d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315608942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.315608942 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |