| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 84.64 | 84.64 | 90.48 | 90.48 | 85.37 | 85.37 | 100.00 | 100.00 | 71.43 | 71.43 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/12.prim_esc_test.2785124057 |
| 87.67 | 3.04 | 93.33 | 2.86 | 85.37 | 0.00 | 100.00 | 0.00 | 82.14 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/1.prim_esc_test.3171432410 |
| 89.41 | 1.74 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.3871592006 |
| 90.55 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/13.prim_esc_test.921281676 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/0.prim_esc_test.1188841706 |
| Name |
|---|
| /workspace/coverage/default/11.prim_esc_test.1362606827 |
| /workspace/coverage/default/14.prim_esc_test.3043890578 |
| /workspace/coverage/default/15.prim_esc_test.3301045496 |
| /workspace/coverage/default/16.prim_esc_test.2540170591 |
| /workspace/coverage/default/17.prim_esc_test.3354968900 |
| /workspace/coverage/default/18.prim_esc_test.3584585745 |
| /workspace/coverage/default/19.prim_esc_test.3541369045 |
| /workspace/coverage/default/2.prim_esc_test.322672666 |
| /workspace/coverage/default/3.prim_esc_test.3722516413 |
| /workspace/coverage/default/4.prim_esc_test.3472982867 |
| /workspace/coverage/default/5.prim_esc_test.2047322178 |
| /workspace/coverage/default/6.prim_esc_test.665111600 |
| /workspace/coverage/default/7.prim_esc_test.3894421679 |
| /workspace/coverage/default/8.prim_esc_test.2536009457 |
| /workspace/coverage/default/9.prim_esc_test.1995670584 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_esc_test.1995670584 | Jul 19 04:22:39 PM PDT 24 | Jul 19 04:22:40 PM PDT 24 | 4880325 ps | ||
| T2 | /workspace/coverage/default/14.prim_esc_test.3043890578 | Jul 19 04:22:53 PM PDT 24 | Jul 19 04:22:56 PM PDT 24 | 5160126 ps | ||
| T3 | /workspace/coverage/default/10.prim_esc_test.3871592006 | Jul 19 04:23:03 PM PDT 24 | Jul 19 04:23:09 PM PDT 24 | 5194715 ps | ||
| T4 | /workspace/coverage/default/0.prim_esc_test.1188841706 | Jul 19 04:21:21 PM PDT 24 | Jul 19 04:21:23 PM PDT 24 | 5112612 ps | ||
| T17 | /workspace/coverage/default/8.prim_esc_test.2536009457 | Jul 19 04:22:55 PM PDT 24 | Jul 19 04:22:58 PM PDT 24 | 4628416 ps | ||
| T6 | /workspace/coverage/default/15.prim_esc_test.3301045496 | Jul 19 04:22:53 PM PDT 24 | Jul 19 04:22:56 PM PDT 24 | 4708528 ps | ||
| T5 | /workspace/coverage/default/6.prim_esc_test.665111600 | Jul 19 04:23:03 PM PDT 24 | Jul 19 04:23:09 PM PDT 24 | 5117488 ps | ||
| T14 | /workspace/coverage/default/12.prim_esc_test.2785124057 | Jul 19 04:23:08 PM PDT 24 | Jul 19 04:23:21 PM PDT 24 | 4799781 ps | ||
| T10 | /workspace/coverage/default/5.prim_esc_test.2047322178 | Jul 19 04:22:46 PM PDT 24 | Jul 19 04:22:48 PM PDT 24 | 5041468 ps | ||
| T18 | /workspace/coverage/default/7.prim_esc_test.3894421679 | Jul 19 04:23:03 PM PDT 24 | Jul 19 04:23:08 PM PDT 24 | 4748969 ps | ||
| T11 | /workspace/coverage/default/2.prim_esc_test.322672666 | Jul 19 04:20:57 PM PDT 24 | Jul 19 04:20:58 PM PDT 24 | 4949334 ps | ||
| T15 | /workspace/coverage/default/19.prim_esc_test.3541369045 | Jul 19 04:22:55 PM PDT 24 | Jul 19 04:22:57 PM PDT 24 | 4861729 ps | ||
| T7 | /workspace/coverage/default/4.prim_esc_test.3472982867 | Jul 19 04:21:21 PM PDT 24 | Jul 19 04:21:23 PM PDT 24 | 4852010 ps | ||
| T13 | /workspace/coverage/default/17.prim_esc_test.3354968900 | Jul 19 04:22:55 PM PDT 24 | Jul 19 04:22:58 PM PDT 24 | 4994712 ps | ||
| T16 | /workspace/coverage/default/16.prim_esc_test.2540170591 | Jul 19 04:22:38 PM PDT 24 | Jul 19 04:22:40 PM PDT 24 | 5043794 ps | ||
| T8 | /workspace/coverage/default/18.prim_esc_test.3584585745 | Jul 19 04:17:08 PM PDT 24 | Jul 19 04:17:09 PM PDT 24 | 5295769 ps | ||
| T19 | /workspace/coverage/default/3.prim_esc_test.3722516413 | Jul 19 04:23:43 PM PDT 24 | Jul 19 04:24:27 PM PDT 24 | 4459983 ps | ||
| T9 | /workspace/coverage/default/13.prim_esc_test.921281676 | Jul 19 04:22:55 PM PDT 24 | Jul 19 04:22:57 PM PDT 24 | 4643572 ps | ||
| T12 | /workspace/coverage/default/1.prim_esc_test.3171432410 | Jul 19 04:23:04 PM PDT 24 | Jul 19 04:23:10 PM PDT 24 | 4797972 ps | ||
| T20 | /workspace/coverage/default/11.prim_esc_test.1362606827 | Jul 19 04:22:38 PM PDT 24 | Jul 19 04:22:40 PM PDT 24 | 5296241 ps |
| Test location | /workspace/coverage/default/12.prim_esc_test.2785124057 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4799781 ps |
| CPU time | 0.38 seconds |
| Started | Jul 19 04:23:08 PM PDT 24 |
| Finished | Jul 19 04:23:21 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-c33a4dc8-d7cc-4b05-884e-f8d20083c630 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785124057 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2785124057 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3171432410 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4797972 ps |
| CPU time | 0.37 seconds |
| Started | Jul 19 04:23:04 PM PDT 24 |
| Finished | Jul 19 04:23:10 PM PDT 24 |
| Peak memory | 145752 kb |
| Host | smart-e2f4324c-4693-492c-b2e0-4e752e6af53f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3171432410 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3171432410 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3871592006 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5194715 ps |
| CPU time | 0.37 seconds |
| Started | Jul 19 04:23:03 PM PDT 24 |
| Finished | Jul 19 04:23:09 PM PDT 24 |
| Peak memory | 145776 kb |
| Host | smart-02e6cda6-a4c2-4177-ab14-0fa4213398e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3871592006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3871592006 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.921281676 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4643572 ps |
| CPU time | 0.36 seconds |
| Started | Jul 19 04:22:55 PM PDT 24 |
| Finished | Jul 19 04:22:57 PM PDT 24 |
| Peak memory | 145760 kb |
| Host | smart-94e2e7dc-dcd7-4ceb-99b9-b845250801a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=921281676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.921281676 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1188841706 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5112612 ps |
| CPU time | 0.4 seconds |
| Started | Jul 19 04:21:21 PM PDT 24 |
| Finished | Jul 19 04:21:23 PM PDT 24 |
| Peak memory | 145936 kb |
| Host | smart-12af0e50-0563-4b32-b893-600cabac7b55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1188841706 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1188841706 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1362606827 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5296241 ps |
| CPU time | 0.39 seconds |
| Started | Jul 19 04:22:38 PM PDT 24 |
| Finished | Jul 19 04:22:40 PM PDT 24 |
| Peak memory | 144488 kb |
| Host | smart-784a12f6-8a2e-47f2-b0f4-6724e3fa9d4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362606827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1362606827 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3043890578 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5160126 ps |
| CPU time | 0.38 seconds |
| Started | Jul 19 04:22:53 PM PDT 24 |
| Finished | Jul 19 04:22:56 PM PDT 24 |
| Peak memory | 145764 kb |
| Host | smart-60e9235a-c8fb-44c7-998c-96aa51431d35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3043890578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3043890578 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3301045496 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4708528 ps |
| CPU time | 0.41 seconds |
| Started | Jul 19 04:22:53 PM PDT 24 |
| Finished | Jul 19 04:22:56 PM PDT 24 |
| Peak memory | 145576 kb |
| Host | smart-77d38b1d-c26f-4713-800f-f94dbded5cd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3301045496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3301045496 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2540170591 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5043794 ps |
| CPU time | 0.4 seconds |
| Started | Jul 19 04:22:38 PM PDT 24 |
| Finished | Jul 19 04:22:40 PM PDT 24 |
| Peak memory | 145652 kb |
| Host | smart-366fe2ee-896a-4733-8bec-2e57e7fe5ef9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540170591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2540170591 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3354968900 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4994712 ps |
| CPU time | 0.43 seconds |
| Started | Jul 19 04:22:55 PM PDT 24 |
| Finished | Jul 19 04:22:58 PM PDT 24 |
| Peak memory | 145796 kb |
| Host | smart-25b1c088-ec9b-4418-8d6c-b930a9ee9942 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3354968900 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3354968900 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3584585745 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5295769 ps |
| CPU time | 0.38 seconds |
| Started | Jul 19 04:17:08 PM PDT 24 |
| Finished | Jul 19 04:17:09 PM PDT 24 |
| Peak memory | 146240 kb |
| Host | smart-b8ad831b-5c4f-45a4-a384-374baec17a3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584585745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3584585745 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3541369045 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4861729 ps |
| CPU time | 0.36 seconds |
| Started | Jul 19 04:22:55 PM PDT 24 |
| Finished | Jul 19 04:22:57 PM PDT 24 |
| Peak memory | 145580 kb |
| Host | smart-bdfa6091-671c-4e0c-9d71-5b0fa1ae1fc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3541369045 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3541369045 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.322672666 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4949334 ps |
| CPU time | 0.38 seconds |
| Started | Jul 19 04:20:57 PM PDT 24 |
| Finished | Jul 19 04:20:58 PM PDT 24 |
| Peak memory | 146208 kb |
| Host | smart-d1df207b-1c9d-413b-96a1-2b649e0d1558 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=322672666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.322672666 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3722516413 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4459983 ps |
| CPU time | 0.41 seconds |
| Started | Jul 19 04:23:43 PM PDT 24 |
| Finished | Jul 19 04:24:27 PM PDT 24 |
| Peak memory | 146324 kb |
| Host | smart-524cbb58-28cf-479f-b777-93604497c0fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3722516413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3722516413 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3472982867 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4852010 ps |
| CPU time | 0.4 seconds |
| Started | Jul 19 04:21:21 PM PDT 24 |
| Finished | Jul 19 04:21:23 PM PDT 24 |
| Peak memory | 145832 kb |
| Host | smart-cab99e20-84c1-4608-a32a-9918fe156a01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3472982867 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3472982867 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2047322178 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5041468 ps |
| CPU time | 0.41 seconds |
| Started | Jul 19 04:22:46 PM PDT 24 |
| Finished | Jul 19 04:22:48 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-c958957d-61cf-4f7c-afcd-e20242e4a375 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2047322178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2047322178 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.665111600 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5117488 ps |
| CPU time | 0.37 seconds |
| Started | Jul 19 04:23:03 PM PDT 24 |
| Finished | Jul 19 04:23:09 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-832240b9-a6dd-4e17-94a5-7ea9e8c16899 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=665111600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.665111600 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3894421679 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4748969 ps |
| CPU time | 0.37 seconds |
| Started | Jul 19 04:23:03 PM PDT 24 |
| Finished | Jul 19 04:23:08 PM PDT 24 |
| Peak memory | 145588 kb |
| Host | smart-42f592e5-5bc0-4a44-b433-38e4a753bff1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3894421679 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3894421679 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2536009457 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4628416 ps |
| CPU time | 0.43 seconds |
| Started | Jul 19 04:22:55 PM PDT 24 |
| Finished | Jul 19 04:22:58 PM PDT 24 |
| Peak memory | 145692 kb |
| Host | smart-28eefff8-dbf5-46c0-bb48-3acbfe0e83bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2536009457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2536009457 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1995670584 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4880325 ps |
| CPU time | 0.36 seconds |
| Started | Jul 19 04:22:39 PM PDT 24 |
| Finished | Jul 19 04:22:40 PM PDT 24 |
| Peak memory | 145520 kb |
| Host | smart-cbe78930-c833-4dd7-97da-28a6a9476249 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995670584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1995670584 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |