| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.23 | 85.23 | 90.48 | 90.48 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 79.07 | 79.07 | 81.48 | 81.48 | /workspace/coverage/default/5.prim_esc_test.3177610768 |
| 88.27 | 3.04 | 93.33 | 2.86 | 85.37 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 83.72 | 4.65 | 81.48 | 0.00 | /workspace/coverage/default/19.prim_esc_test.571843985 |
| 89.41 | 1.14 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.2549707166 |
| 90.55 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/8.prim_esc_test.2375957906 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/14.prim_esc_test.1779785678 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1018754973 |
| /workspace/coverage/default/1.prim_esc_test.3226466919 |
| /workspace/coverage/default/11.prim_esc_test.1705631053 |
| /workspace/coverage/default/12.prim_esc_test.1446925194 |
| /workspace/coverage/default/13.prim_esc_test.979885623 |
| /workspace/coverage/default/15.prim_esc_test.3336932875 |
| /workspace/coverage/default/16.prim_esc_test.1061550265 |
| /workspace/coverage/default/17.prim_esc_test.3239935983 |
| /workspace/coverage/default/18.prim_esc_test.1764922764 |
| /workspace/coverage/default/2.prim_esc_test.748127985 |
| /workspace/coverage/default/3.prim_esc_test.3300670839 |
| /workspace/coverage/default/4.prim_esc_test.2384972969 |
| /workspace/coverage/default/6.prim_esc_test.3883815031 |
| /workspace/coverage/default/7.prim_esc_test.4192620803 |
| /workspace/coverage/default/9.prim_esc_test.3536245225 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/5.prim_esc_test.3177610768 | Jul 20 04:24:34 PM PDT 24 | Jul 20 04:24:35 PM PDT 24 | 4642972 ps | ||
| T2 | /workspace/coverage/default/1.prim_esc_test.3226466919 | Jul 20 04:24:21 PM PDT 24 | Jul 20 04:24:22 PM PDT 24 | 4828310 ps | ||
| T3 | /workspace/coverage/default/7.prim_esc_test.4192620803 | Jul 20 04:23:51 PM PDT 24 | Jul 20 04:23:52 PM PDT 24 | 4250362 ps | ||
| T5 | /workspace/coverage/default/14.prim_esc_test.1779785678 | Jul 20 04:23:37 PM PDT 24 | Jul 20 04:23:37 PM PDT 24 | 5191035 ps | ||
| T13 | /workspace/coverage/default/6.prim_esc_test.3883815031 | Jul 20 04:24:11 PM PDT 24 | Jul 20 04:24:12 PM PDT 24 | 4507275 ps | ||
| T4 | /workspace/coverage/default/12.prim_esc_test.1446925194 | Jul 20 04:22:01 PM PDT 24 | Jul 20 04:22:01 PM PDT 24 | 4953235 ps | ||
| T10 | /workspace/coverage/default/16.prim_esc_test.1061550265 | Jul 20 04:24:29 PM PDT 24 | Jul 20 04:24:30 PM PDT 24 | 4624202 ps | ||
| T14 | /workspace/coverage/default/4.prim_esc_test.2384972969 | Jul 20 04:21:38 PM PDT 24 | Jul 20 04:21:39 PM PDT 24 | 5051778 ps | ||
| T11 | /workspace/coverage/default/3.prim_esc_test.3300670839 | Jul 20 04:19:48 PM PDT 24 | Jul 20 04:19:49 PM PDT 24 | 4821534 ps | ||
| T15 | /workspace/coverage/default/11.prim_esc_test.1705631053 | Jul 20 04:23:51 PM PDT 24 | Jul 20 04:23:52 PM PDT 24 | 5447565 ps | ||
| T12 | /workspace/coverage/default/8.prim_esc_test.2375957906 | Jul 20 04:23:31 PM PDT 24 | Jul 20 04:23:32 PM PDT 24 | 5071766 ps | ||
| T8 | /workspace/coverage/default/19.prim_esc_test.571843985 | Jul 20 04:23:46 PM PDT 24 | Jul 20 04:23:47 PM PDT 24 | 5280596 ps | ||
| T16 | /workspace/coverage/default/0.prim_esc_test.1018754973 | Jul 20 04:23:11 PM PDT 24 | Jul 20 04:23:11 PM PDT 24 | 4595349 ps | ||
| T9 | /workspace/coverage/default/9.prim_esc_test.3536245225 | Jul 20 04:23:35 PM PDT 24 | Jul 20 04:23:36 PM PDT 24 | 4394735 ps | ||
| T6 | /workspace/coverage/default/15.prim_esc_test.3336932875 | Jul 20 04:23:22 PM PDT 24 | Jul 20 04:23:23 PM PDT 24 | 4995454 ps | ||
| T17 | /workspace/coverage/default/17.prim_esc_test.3239935983 | Jul 20 04:24:30 PM PDT 24 | Jul 20 04:24:31 PM PDT 24 | 4753409 ps | ||
| T18 | /workspace/coverage/default/2.prim_esc_test.748127985 | Jul 20 04:22:12 PM PDT 24 | Jul 20 04:22:13 PM PDT 24 | 4904752 ps | ||
| T7 | /workspace/coverage/default/10.prim_esc_test.2549707166 | Jul 20 04:19:51 PM PDT 24 | Jul 20 04:19:52 PM PDT 24 | 5062826 ps | ||
| T19 | /workspace/coverage/default/18.prim_esc_test.1764922764 | Jul 20 04:24:13 PM PDT 24 | Jul 20 04:24:14 PM PDT 24 | 4483561 ps | ||
| T20 | /workspace/coverage/default/13.prim_esc_test.979885623 | Jul 20 04:23:51 PM PDT 24 | Jul 20 04:23:52 PM PDT 24 | 4957286 ps |
| Test location | /workspace/coverage/default/5.prim_esc_test.3177610768 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4642972 ps |
| CPU time | 0.37 seconds |
| Started | Jul 20 04:24:34 PM PDT 24 |
| Finished | Jul 20 04:24:35 PM PDT 24 |
| Peak memory | 146820 kb |
| Host | smart-0f5ec57f-0a30-417b-b2bb-e033f95699d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3177610768 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3177610768 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.571843985 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5280596 ps |
| CPU time | 0.39 seconds |
| Started | Jul 20 04:23:46 PM PDT 24 |
| Finished | Jul 20 04:23:47 PM PDT 24 |
| Peak memory | 144668 kb |
| Host | smart-94426b96-338a-4020-b294-591d44e692b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=571843985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.571843985 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2549707166 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5062826 ps |
| CPU time | 0.4 seconds |
| Started | Jul 20 04:19:51 PM PDT 24 |
| Finished | Jul 20 04:19:52 PM PDT 24 |
| Peak memory | 145716 kb |
| Host | smart-f57c3404-5dec-4b65-beef-21d62c42688e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2549707166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2549707166 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2375957906 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5071766 ps |
| CPU time | 0.42 seconds |
| Started | Jul 20 04:23:31 PM PDT 24 |
| Finished | Jul 20 04:23:32 PM PDT 24 |
| Peak memory | 146080 kb |
| Host | smart-a6c626b0-793e-4183-8277-412e6282b55b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2375957906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2375957906 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1779785678 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5191035 ps |
| CPU time | 0.36 seconds |
| Started | Jul 20 04:23:37 PM PDT 24 |
| Finished | Jul 20 04:23:37 PM PDT 24 |
| Peak memory | 145736 kb |
| Host | smart-7344d30a-c70b-4e35-9549-4d4d7c86e6d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1779785678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1779785678 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1018754973 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4595349 ps |
| CPU time | 0.38 seconds |
| Started | Jul 20 04:23:11 PM PDT 24 |
| Finished | Jul 20 04:23:11 PM PDT 24 |
| Peak memory | 146028 kb |
| Host | smart-1f32f7f4-6061-4073-a670-3c313f495b47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1018754973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1018754973 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3226466919 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4828310 ps |
| CPU time | 0.47 seconds |
| Started | Jul 20 04:24:21 PM PDT 24 |
| Finished | Jul 20 04:24:22 PM PDT 24 |
| Peak memory | 146200 kb |
| Host | smart-99b0bdd7-02b1-40fc-ae6d-5dd475a0e1ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3226466919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3226466919 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.1705631053 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5447565 ps |
| CPU time | 0.37 seconds |
| Started | Jul 20 04:23:51 PM PDT 24 |
| Finished | Jul 20 04:23:52 PM PDT 24 |
| Peak memory | 145632 kb |
| Host | smart-7d97765f-94b8-43a1-88d6-7add909a1631 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705631053 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1705631053 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1446925194 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4953235 ps |
| CPU time | 0.38 seconds |
| Started | Jul 20 04:22:01 PM PDT 24 |
| Finished | Jul 20 04:22:01 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-a4dfc594-d2cb-4461-a2c8-61d9a5c4110b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1446925194 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1446925194 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.979885623 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4957286 ps |
| CPU time | 0.37 seconds |
| Started | Jul 20 04:23:51 PM PDT 24 |
| Finished | Jul 20 04:23:52 PM PDT 24 |
| Peak memory | 145608 kb |
| Host | smart-11ee7427-bdd2-4a62-9686-8085bdb5d9fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=979885623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.979885623 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3336932875 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4995454 ps |
| CPU time | 0.4 seconds |
| Started | Jul 20 04:23:22 PM PDT 24 |
| Finished | Jul 20 04:23:23 PM PDT 24 |
| Peak memory | 146160 kb |
| Host | smart-af68433b-57a7-448b-abaf-7505aa2274d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3336932875 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3336932875 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1061550265 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4624202 ps |
| CPU time | 0.36 seconds |
| Started | Jul 20 04:24:29 PM PDT 24 |
| Finished | Jul 20 04:24:30 PM PDT 24 |
| Peak memory | 145724 kb |
| Host | smart-e709fa76-75e0-4cb1-8632-4f16f05a7879 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1061550265 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1061550265 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3239935983 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4753409 ps |
| CPU time | 0.38 seconds |
| Started | Jul 20 04:24:30 PM PDT 24 |
| Finished | Jul 20 04:24:31 PM PDT 24 |
| Peak memory | 145780 kb |
| Host | smart-8b902ecd-9cd3-4de9-9b83-339d1581c913 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3239935983 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3239935983 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1764922764 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4483561 ps |
| CPU time | 0.4 seconds |
| Started | Jul 20 04:24:13 PM PDT 24 |
| Finished | Jul 20 04:24:14 PM PDT 24 |
| Peak memory | 146360 kb |
| Host | smart-020181d4-78f8-4322-a424-65dd15c799ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764922764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1764922764 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.748127985 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4904752 ps |
| CPU time | 0.38 seconds |
| Started | Jul 20 04:22:12 PM PDT 24 |
| Finished | Jul 20 04:22:13 PM PDT 24 |
| Peak memory | 145984 kb |
| Host | smart-9814704d-6c2e-471b-89ba-6b08ecef7319 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=748127985 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.748127985 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3300670839 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4821534 ps |
| CPU time | 0.4 seconds |
| Started | Jul 20 04:19:48 PM PDT 24 |
| Finished | Jul 20 04:19:49 PM PDT 24 |
| Peak memory | 146248 kb |
| Host | smart-4b13811f-0c2a-4a12-b2d5-55b2a419c38f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3300670839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3300670839 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2384972969 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5051778 ps |
| CPU time | 0.38 seconds |
| Started | Jul 20 04:21:38 PM PDT 24 |
| Finished | Jul 20 04:21:39 PM PDT 24 |
| Peak memory | 145988 kb |
| Host | smart-71eb2925-de57-4462-bc27-e466a5233d13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384972969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2384972969 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3883815031 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4507275 ps |
| CPU time | 0.37 seconds |
| Started | Jul 20 04:24:11 PM PDT 24 |
| Finished | Jul 20 04:24:12 PM PDT 24 |
| Peak memory | 146816 kb |
| Host | smart-dd3f97ed-ee5c-471e-96ca-24a27ef43686 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883815031 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3883815031 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.4192620803 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4250362 ps |
| CPU time | 0.37 seconds |
| Started | Jul 20 04:23:51 PM PDT 24 |
| Finished | Jul 20 04:23:52 PM PDT 24 |
| Peak memory | 145620 kb |
| Host | smart-874e286e-bf17-4364-8e0d-dfed9694c36a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4192620803 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4192620803 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3536245225 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4394735 ps |
| CPU time | 0.42 seconds |
| Started | Jul 20 04:23:35 PM PDT 24 |
| Finished | Jul 20 04:23:36 PM PDT 24 |
| Peak memory | 146084 kb |
| Host | smart-e638347b-b908-4046-899c-fc9e426c5da0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3536245225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3536245225 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |