Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.94 85.94 92.38 92.38 85.37 85.37 100.00 100.00 75.00 75.00 81.40 81.40 81.48 81.48 /workspace/coverage/default/18.prim_esc_test.1555729977
87.67 1.74 93.33 0.95 85.37 0.00 100.00 0.00 82.14 7.14 83.72 2.33 81.48 0.00 /workspace/coverage/default/0.prim_esc_test.4116990911
89.41 1.74 94.29 0.95 85.37 0.00 100.00 0.00 89.29 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/5.prim_esc_test.1003077433
90.55 1.14 95.24 0.95 85.37 0.00 100.00 0.00 92.86 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/11.prim_esc_test.3673634430
91.15 0.60 95.24 0.00 85.37 0.00 100.00 0.00 96.43 3.57 88.37 0.00 81.48 0.00 /workspace/coverage/default/13.prim_esc_test.2474409802

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.283028508
/workspace/coverage/default/10.prim_esc_test.3925657351
/workspace/coverage/default/12.prim_esc_test.4033199772
/workspace/coverage/default/14.prim_esc_test.3603801033
/workspace/coverage/default/15.prim_esc_test.2672635088
/workspace/coverage/default/16.prim_esc_test.1150926232
/workspace/coverage/default/17.prim_esc_test.1747852509
/workspace/coverage/default/19.prim_esc_test.2694314100
/workspace/coverage/default/2.prim_esc_test.2969659280
/workspace/coverage/default/3.prim_esc_test.1266199676
/workspace/coverage/default/4.prim_esc_test.3972837737
/workspace/coverage/default/6.prim_esc_test.2849936428
/workspace/coverage/default/7.prim_esc_test.1459185830
/workspace/coverage/default/8.prim_esc_test.1010840439
/workspace/coverage/default/9.prim_esc_test.4110403441



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/2.prim_esc_test.2969659280 Jul 21 04:18:09 PM PDT 24 Jul 21 04:18:11 PM PDT 24 4912978 ps
T2 /workspace/coverage/default/4.prim_esc_test.3972837737 Jul 21 04:18:08 PM PDT 24 Jul 21 04:18:10 PM PDT 24 5022387 ps
T3 /workspace/coverage/default/9.prim_esc_test.4110403441 Jul 21 04:23:05 PM PDT 24 Jul 21 04:23:06 PM PDT 24 4499760 ps
T4 /workspace/coverage/default/15.prim_esc_test.2672635088 Jul 21 04:19:01 PM PDT 24 Jul 21 04:19:02 PM PDT 24 4318996 ps
T9 /workspace/coverage/default/0.prim_esc_test.4116990911 Jul 21 04:18:09 PM PDT 24 Jul 21 04:18:11 PM PDT 24 4862247 ps
T5 /workspace/coverage/default/7.prim_esc_test.1459185830 Jul 21 04:19:09 PM PDT 24 Jul 21 04:19:10 PM PDT 24 4916213 ps
T8 /workspace/coverage/default/3.prim_esc_test.1266199676 Jul 21 04:18:09 PM PDT 24 Jul 21 04:18:10 PM PDT 24 4705724 ps
T10 /workspace/coverage/default/17.prim_esc_test.1747852509 Jul 21 04:18:58 PM PDT 24 Jul 21 04:18:59 PM PDT 24 5119476 ps
T13 /workspace/coverage/default/12.prim_esc_test.4033199772 Jul 21 04:19:33 PM PDT 24 Jul 21 04:19:33 PM PDT 24 4451743 ps
T7 /workspace/coverage/default/18.prim_esc_test.1555729977 Jul 21 04:19:05 PM PDT 24 Jul 21 04:19:06 PM PDT 24 4733164 ps
T6 /workspace/coverage/default/5.prim_esc_test.1003077433 Jul 21 04:18:09 PM PDT 24 Jul 21 04:18:10 PM PDT 24 4724025 ps
T14 /workspace/coverage/default/8.prim_esc_test.1010840439 Jul 21 04:18:08 PM PDT 24 Jul 21 04:18:10 PM PDT 24 4899285 ps
T15 /workspace/coverage/default/16.prim_esc_test.1150926232 Jul 21 04:19:45 PM PDT 24 Jul 21 04:19:46 PM PDT 24 4840134 ps
T16 /workspace/coverage/default/19.prim_esc_test.2694314100 Jul 21 04:18:08 PM PDT 24 Jul 21 04:18:09 PM PDT 24 4622796 ps
T12 /workspace/coverage/default/11.prim_esc_test.3673634430 Jul 21 04:19:45 PM PDT 24 Jul 21 04:19:46 PM PDT 24 4892474 ps
T11 /workspace/coverage/default/13.prim_esc_test.2474409802 Jul 21 04:21:21 PM PDT 24 Jul 21 04:21:21 PM PDT 24 5063022 ps
T17 /workspace/coverage/default/10.prim_esc_test.3925657351 Jul 21 04:19:36 PM PDT 24 Jul 21 04:19:37 PM PDT 24 4801827 ps
T18 /workspace/coverage/default/1.prim_esc_test.283028508 Jul 21 04:18:09 PM PDT 24 Jul 21 04:18:10 PM PDT 24 4877236 ps
T19 /workspace/coverage/default/14.prim_esc_test.3603801033 Jul 21 04:22:57 PM PDT 24 Jul 21 04:22:58 PM PDT 24 4086613 ps
T20 /workspace/coverage/default/6.prim_esc_test.2849936428 Jul 21 04:19:09 PM PDT 24 Jul 21 04:19:10 PM PDT 24 4734261 ps

Test location /workspace/coverage/default/18.prim_esc_test.1555729977
Short name T7
Test name
Test status
Simulation time 4733164 ps
CPU time 0.37 seconds
Started Jul 21 04:19:05 PM PDT 24
Finished Jul 21 04:19:06 PM PDT 24
Peak memory 146032 kb
Host smart-0fdb643c-6c0c-4023-840d-9591c16e451e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555729977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1555729977
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.4116990911
Short name T9
Test name
Test status
Simulation time 4862247 ps
CPU time 0.38 seconds
Started Jul 21 04:18:09 PM PDT 24
Finished Jul 21 04:18:11 PM PDT 24
Peak memory 145624 kb
Host smart-b4c90d84-8a1e-4e35-9cfc-3d940420b70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116990911 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.4116990911
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.1003077433
Short name T6
Test name
Test status
Simulation time 4724025 ps
CPU time 0.37 seconds
Started Jul 21 04:18:09 PM PDT 24
Finished Jul 21 04:18:10 PM PDT 24
Peak memory 145624 kb
Host smart-240427f6-70b5-4170-be99-31040f6488d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003077433 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1003077433
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.3673634430
Short name T12
Test name
Test status
Simulation time 4892474 ps
CPU time 0.38 seconds
Started Jul 21 04:19:45 PM PDT 24
Finished Jul 21 04:19:46 PM PDT 24
Peak memory 146272 kb
Host smart-d1562464-2d1d-42ae-adc7-60fa284333c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673634430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3673634430
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.2474409802
Short name T11
Test name
Test status
Simulation time 5063022 ps
CPU time 0.38 seconds
Started Jul 21 04:21:21 PM PDT 24
Finished Jul 21 04:21:21 PM PDT 24
Peak memory 146144 kb
Host smart-aaa935b8-9ecb-49c0-a3f3-28c2e2362ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474409802 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2474409802
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.283028508
Short name T18
Test name
Test status
Simulation time 4877236 ps
CPU time 0.37 seconds
Started Jul 21 04:18:09 PM PDT 24
Finished Jul 21 04:18:10 PM PDT 24
Peak memory 145616 kb
Host smart-2ae7bbe8-32d5-4523-a3a1-877335021b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283028508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.283028508
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.3925657351
Short name T17
Test name
Test status
Simulation time 4801827 ps
CPU time 0.39 seconds
Started Jul 21 04:19:36 PM PDT 24
Finished Jul 21 04:19:37 PM PDT 24
Peak memory 146048 kb
Host smart-25bf783d-f4c0-49f3-a5ea-a71f69aec347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925657351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3925657351
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.4033199772
Short name T13
Test name
Test status
Simulation time 4451743 ps
CPU time 0.38 seconds
Started Jul 21 04:19:33 PM PDT 24
Finished Jul 21 04:19:33 PM PDT 24
Peak memory 145880 kb
Host smart-4ecf5db3-080c-4a19-b092-a2c06c9b1bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033199772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.4033199772
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.3603801033
Short name T19
Test name
Test status
Simulation time 4086613 ps
CPU time 0.37 seconds
Started Jul 21 04:22:57 PM PDT 24
Finished Jul 21 04:22:58 PM PDT 24
Peak memory 146056 kb
Host smart-560adf46-8472-4bec-9941-992dc56e0bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603801033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3603801033
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.2672635088
Short name T4
Test name
Test status
Simulation time 4318996 ps
CPU time 0.38 seconds
Started Jul 21 04:19:01 PM PDT 24
Finished Jul 21 04:19:02 PM PDT 24
Peak memory 145932 kb
Host smart-1e20e500-f706-41c4-9fda-aa646baa4620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672635088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2672635088
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1150926232
Short name T15
Test name
Test status
Simulation time 4840134 ps
CPU time 0.38 seconds
Started Jul 21 04:19:45 PM PDT 24
Finished Jul 21 04:19:46 PM PDT 24
Peak memory 146032 kb
Host smart-161c73e9-8396-4fe1-917b-12c826ca1d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150926232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1150926232
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.1747852509
Short name T10
Test name
Test status
Simulation time 5119476 ps
CPU time 0.38 seconds
Started Jul 21 04:18:58 PM PDT 24
Finished Jul 21 04:18:59 PM PDT 24
Peak memory 146976 kb
Host smart-2f4bd02a-a60d-4b25-a574-c801094b3052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747852509 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1747852509
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.2694314100
Short name T16
Test name
Test status
Simulation time 4622796 ps
CPU time 0.37 seconds
Started Jul 21 04:18:08 PM PDT 24
Finished Jul 21 04:18:09 PM PDT 24
Peak memory 145792 kb
Host smart-672657b7-01c7-4e4c-9be6-bc2de33d9f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694314100 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2694314100
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.2969659280
Short name T1
Test name
Test status
Simulation time 4912978 ps
CPU time 0.38 seconds
Started Jul 21 04:18:09 PM PDT 24
Finished Jul 21 04:18:11 PM PDT 24
Peak memory 145624 kb
Host smart-1376f10e-4d97-47ec-8ad6-9916b4d9db7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969659280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2969659280
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.1266199676
Short name T8
Test name
Test status
Simulation time 4705724 ps
CPU time 0.38 seconds
Started Jul 21 04:18:09 PM PDT 24
Finished Jul 21 04:18:10 PM PDT 24
Peak memory 146272 kb
Host smart-07740c86-2880-446e-89f6-c03f229e9a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266199676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1266199676
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.3972837737
Short name T2
Test name
Test status
Simulation time 5022387 ps
CPU time 0.38 seconds
Started Jul 21 04:18:08 PM PDT 24
Finished Jul 21 04:18:10 PM PDT 24
Peak memory 146836 kb
Host smart-205687cb-7f9c-466a-aed6-9bf7e59051e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972837737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3972837737
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.2849936428
Short name T20
Test name
Test status
Simulation time 4734261 ps
CPU time 0.44 seconds
Started Jul 21 04:19:09 PM PDT 24
Finished Jul 21 04:19:10 PM PDT 24
Peak memory 144764 kb
Host smart-bfe0390f-62a5-4443-8c6c-c3bad94d55a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849936428 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2849936428
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.1459185830
Short name T5
Test name
Test status
Simulation time 4916213 ps
CPU time 0.45 seconds
Started Jul 21 04:19:09 PM PDT 24
Finished Jul 21 04:19:10 PM PDT 24
Peak memory 144796 kb
Host smart-83ecba5f-4829-4495-80dc-7120ac63488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459185830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1459185830
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.1010840439
Short name T14
Test name
Test status
Simulation time 4899285 ps
CPU time 0.38 seconds
Started Jul 21 04:18:08 PM PDT 24
Finished Jul 21 04:18:10 PM PDT 24
Peak memory 146272 kb
Host smart-aade57dc-b009-4f5c-b2ce-4f54b712c62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010840439 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1010840439
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.4110403441
Short name T3
Test name
Test status
Simulation time 4499760 ps
CPU time 0.36 seconds
Started Jul 21 04:23:05 PM PDT 24
Finished Jul 21 04:23:06 PM PDT 24
Peak memory 145960 kb
Host smart-919f4509-dfbe-4e43-9897-9481ca0b3867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110403441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.4110403441
Directory /workspace/9.prim_esc_test/latest
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