Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.15 95.24 85.37 100.00 96.43 88.37 81.48


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.23 85.23 90.48 90.48 85.37 85.37 100.00 100.00 75.00 75.00 79.07 79.07 81.48 81.48 /workspace/coverage/default/15.prim_esc_test.3121315455
87.67 2.44 93.33 2.86 85.37 0.00 100.00 0.00 82.14 7.14 83.72 4.65 81.48 0.00 /workspace/coverage/default/13.prim_esc_test.752317640
89.41 1.74 94.29 0.95 85.37 0.00 100.00 0.00 89.29 7.14 86.05 2.33 81.48 0.00 /workspace/coverage/default/17.prim_esc_test.1361183646
90.55 1.14 95.24 0.95 85.37 0.00 100.00 0.00 92.86 3.57 88.37 2.33 81.48 0.00 /workspace/coverage/default/0.prim_esc_test.1011859151
91.15 0.60 95.24 0.00 85.37 0.00 100.00 0.00 96.43 3.57 88.37 0.00 81.48 0.00 /workspace/coverage/default/10.prim_esc_test.72923168

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.3217276151
/workspace/coverage/default/11.prim_esc_test.3624152842
/workspace/coverage/default/12.prim_esc_test.1712125936
/workspace/coverage/default/14.prim_esc_test.3374527782
/workspace/coverage/default/16.prim_esc_test.3345592186
/workspace/coverage/default/18.prim_esc_test.852251510
/workspace/coverage/default/19.prim_esc_test.2661568692
/workspace/coverage/default/2.prim_esc_test.2140215872
/workspace/coverage/default/3.prim_esc_test.1922311430
/workspace/coverage/default/4.prim_esc_test.1323779735
/workspace/coverage/default/5.prim_esc_test.397463344
/workspace/coverage/default/6.prim_esc_test.4088659176
/workspace/coverage/default/7.prim_esc_test.1344341891
/workspace/coverage/default/8.prim_esc_test.3236474831
/workspace/coverage/default/9.prim_esc_test.2766969844



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/11.prim_esc_test.3624152842 Jul 22 05:19:21 PM PDT 24 Jul 22 05:19:22 PM PDT 24 4925248 ps
T2 /workspace/coverage/default/17.prim_esc_test.1361183646 Jul 22 05:19:20 PM PDT 24 Jul 22 05:19:21 PM PDT 24 4487549 ps
T3 /workspace/coverage/default/2.prim_esc_test.2140215872 Jul 22 05:19:12 PM PDT 24 Jul 22 05:19:13 PM PDT 24 4813038 ps
T4 /workspace/coverage/default/5.prim_esc_test.397463344 Jul 22 05:19:12 PM PDT 24 Jul 22 05:19:13 PM PDT 24 5172435 ps
T6 /workspace/coverage/default/8.prim_esc_test.3236474831 Jul 22 05:19:15 PM PDT 24 Jul 22 05:19:16 PM PDT 24 5110765 ps
T7 /workspace/coverage/default/1.prim_esc_test.3217276151 Jul 22 05:19:10 PM PDT 24 Jul 22 05:19:11 PM PDT 24 4648404 ps
T5 /workspace/coverage/default/15.prim_esc_test.3121315455 Jul 22 05:19:26 PM PDT 24 Jul 22 05:19:27 PM PDT 24 4476896 ps
T14 /workspace/coverage/default/4.prim_esc_test.1323779735 Jul 22 05:19:11 PM PDT 24 Jul 22 05:19:12 PM PDT 24 4378759 ps
T10 /workspace/coverage/default/10.prim_esc_test.72923168 Jul 22 05:19:20 PM PDT 24 Jul 22 05:19:21 PM PDT 24 4887482 ps
T11 /workspace/coverage/default/16.prim_esc_test.3345592186 Jul 22 05:19:20 PM PDT 24 Jul 22 05:19:21 PM PDT 24 4894481 ps
T12 /workspace/coverage/default/14.prim_esc_test.3374527782 Jul 22 05:19:23 PM PDT 24 Jul 22 05:19:24 PM PDT 24 4730717 ps
T15 /workspace/coverage/default/3.prim_esc_test.1922311430 Jul 22 05:19:11 PM PDT 24 Jul 22 05:19:12 PM PDT 24 5179061 ps
T16 /workspace/coverage/default/9.prim_esc_test.2766969844 Jul 22 05:19:12 PM PDT 24 Jul 22 05:19:13 PM PDT 24 5225588 ps
T13 /workspace/coverage/default/0.prim_esc_test.1011859151 Jul 22 05:19:10 PM PDT 24 Jul 22 05:19:11 PM PDT 24 4820455 ps
T17 /workspace/coverage/default/7.prim_esc_test.1344341891 Jul 22 05:19:11 PM PDT 24 Jul 22 05:19:12 PM PDT 24 4742910 ps
T9 /workspace/coverage/default/6.prim_esc_test.4088659176 Jul 22 05:19:12 PM PDT 24 Jul 22 05:19:12 PM PDT 24 4897851 ps
T18 /workspace/coverage/default/12.prim_esc_test.1712125936 Jul 22 05:19:21 PM PDT 24 Jul 22 05:19:22 PM PDT 24 4429700 ps
T19 /workspace/coverage/default/18.prim_esc_test.852251510 Jul 22 05:19:20 PM PDT 24 Jul 22 05:19:21 PM PDT 24 4724366 ps
T20 /workspace/coverage/default/19.prim_esc_test.2661568692 Jul 22 05:19:19 PM PDT 24 Jul 22 05:19:20 PM PDT 24 4398598 ps
T8 /workspace/coverage/default/13.prim_esc_test.752317640 Jul 22 05:19:20 PM PDT 24 Jul 22 05:19:21 PM PDT 24 4491859 ps

Test location /workspace/coverage/default/15.prim_esc_test.3121315455
Short name T5
Test name
Test status
Simulation time 4476896 ps
CPU time 0.36 seconds
Started Jul 22 05:19:26 PM PDT 24
Finished Jul 22 05:19:27 PM PDT 24
Peak memory 146216 kb
Host smart-7f6c4512-c10f-4cea-9e86-8f2e6c2090d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121315455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3121315455
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.752317640
Short name T8
Test name
Test status
Simulation time 4491859 ps
CPU time 0.37 seconds
Started Jul 22 05:19:20 PM PDT 24
Finished Jul 22 05:19:21 PM PDT 24
Peak memory 146020 kb
Host smart-192ad5be-1982-4897-aaea-3c90c968b0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752317640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.752317640
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.1361183646
Short name T2
Test name
Test status
Simulation time 4487549 ps
CPU time 0.39 seconds
Started Jul 22 05:19:20 PM PDT 24
Finished Jul 22 05:19:21 PM PDT 24
Peak memory 146148 kb
Host smart-ac0afd8c-0c4d-4f2a-9bde-71aab6e0f46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361183646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1361183646
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.1011859151
Short name T13
Test name
Test status
Simulation time 4820455 ps
CPU time 0.37 seconds
Started Jul 22 05:19:10 PM PDT 24
Finished Jul 22 05:19:11 PM PDT 24
Peak memory 146148 kb
Host smart-2cc8d527-ddd1-4dc9-abbc-4c37c6680847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011859151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1011859151
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.72923168
Short name T10
Test name
Test status
Simulation time 4887482 ps
CPU time 0.38 seconds
Started Jul 22 05:19:20 PM PDT 24
Finished Jul 22 05:19:21 PM PDT 24
Peak memory 146152 kb
Host smart-46695150-7239-429e-b7ea-1b479f908038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72923168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.72923168
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.3217276151
Short name T7
Test name
Test status
Simulation time 4648404 ps
CPU time 0.37 seconds
Started Jul 22 05:19:10 PM PDT 24
Finished Jul 22 05:19:11 PM PDT 24
Peak memory 146128 kb
Host smart-62343169-f862-4009-aed5-174b3f562935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217276151 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3217276151
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.3624152842
Short name T1
Test name
Test status
Simulation time 4925248 ps
CPU time 0.38 seconds
Started Jul 22 05:19:21 PM PDT 24
Finished Jul 22 05:19:22 PM PDT 24
Peak memory 146160 kb
Host smart-949d64ef-8ae9-4db9-aec8-de2b9bfc4eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624152842 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3624152842
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.1712125936
Short name T18
Test name
Test status
Simulation time 4429700 ps
CPU time 0.38 seconds
Started Jul 22 05:19:21 PM PDT 24
Finished Jul 22 05:19:22 PM PDT 24
Peak memory 146168 kb
Host smart-63de2cf7-6ae0-4c73-96e5-79f556b05c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712125936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1712125936
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.3374527782
Short name T12
Test name
Test status
Simulation time 4730717 ps
CPU time 0.39 seconds
Started Jul 22 05:19:23 PM PDT 24
Finished Jul 22 05:19:24 PM PDT 24
Peak memory 146160 kb
Host smart-e29fe699-0d4d-4f9a-a9f0-0fee30a86c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374527782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3374527782
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.3345592186
Short name T11
Test name
Test status
Simulation time 4894481 ps
CPU time 0.38 seconds
Started Jul 22 05:19:20 PM PDT 24
Finished Jul 22 05:19:21 PM PDT 24
Peak memory 146172 kb
Host smart-fe473b05-0bde-4cd6-bd55-a26e45ad55b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345592186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3345592186
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.852251510
Short name T19
Test name
Test status
Simulation time 4724366 ps
CPU time 0.37 seconds
Started Jul 22 05:19:20 PM PDT 24
Finished Jul 22 05:19:21 PM PDT 24
Peak memory 146000 kb
Host smart-8c55559c-234f-47e4-9efa-ecf147e514c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852251510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.852251510
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.2661568692
Short name T20
Test name
Test status
Simulation time 4398598 ps
CPU time 0.38 seconds
Started Jul 22 05:19:19 PM PDT 24
Finished Jul 22 05:19:20 PM PDT 24
Peak memory 146184 kb
Host smart-160316dd-407e-489b-ac75-646506be22a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661568692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2661568692
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.2140215872
Short name T3
Test name
Test status
Simulation time 4813038 ps
CPU time 0.37 seconds
Started Jul 22 05:19:12 PM PDT 24
Finished Jul 22 05:19:13 PM PDT 24
Peak memory 146168 kb
Host smart-50513ccd-0e4f-495c-9502-532ca11793c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140215872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2140215872
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.1922311430
Short name T15
Test name
Test status
Simulation time 5179061 ps
CPU time 0.39 seconds
Started Jul 22 05:19:11 PM PDT 24
Finished Jul 22 05:19:12 PM PDT 24
Peak memory 146200 kb
Host smart-49f541c4-02ad-4df7-ab8c-01ccd91d57a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922311430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1922311430
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.1323779735
Short name T14
Test name
Test status
Simulation time 4378759 ps
CPU time 0.37 seconds
Started Jul 22 05:19:11 PM PDT 24
Finished Jul 22 05:19:12 PM PDT 24
Peak memory 146008 kb
Host smart-95adf67d-42bb-487c-bb0e-0ff96321a88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323779735 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1323779735
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.397463344
Short name T4
Test name
Test status
Simulation time 5172435 ps
CPU time 0.38 seconds
Started Jul 22 05:19:12 PM PDT 24
Finished Jul 22 05:19:13 PM PDT 24
Peak memory 146144 kb
Host smart-258d8e37-9f3b-4deb-a4f5-b84bb0468ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397463344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.397463344
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.4088659176
Short name T9
Test name
Test status
Simulation time 4897851 ps
CPU time 0.36 seconds
Started Jul 22 05:19:12 PM PDT 24
Finished Jul 22 05:19:12 PM PDT 24
Peak memory 146084 kb
Host smart-44cdcc09-ef05-4e21-bbee-600790f8f072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088659176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4088659176
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.1344341891
Short name T17
Test name
Test status
Simulation time 4742910 ps
CPU time 0.37 seconds
Started Jul 22 05:19:11 PM PDT 24
Finished Jul 22 05:19:12 PM PDT 24
Peak memory 145932 kb
Host smart-dc76d7c2-3da7-4141-8be3-9cb1168f1527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344341891 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1344341891
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.3236474831
Short name T6
Test name
Test status
Simulation time 5110765 ps
CPU time 0.38 seconds
Started Jul 22 05:19:15 PM PDT 24
Finished Jul 22 05:19:16 PM PDT 24
Peak memory 146160 kb
Host smart-dc766a92-544a-489e-bd2f-ca27fdaf375b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236474831 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3236474831
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.2766969844
Short name T16
Test name
Test status
Simulation time 5225588 ps
CPU time 0.37 seconds
Started Jul 22 05:19:12 PM PDT 24
Finished Jul 22 05:19:13 PM PDT 24
Peak memory 146080 kb
Host smart-45e33606-9bf8-46ad-a484-50ff0f3a1897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766969844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2766969844
Directory /workspace/9.prim_esc_test/latest
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