| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.15 | 95.24 | 85.37 | 100.00 | 96.43 | 88.37 | 81.48 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.13 | 86.13 | 92.38 | 92.38 | 82.93 | 82.93 | 100.00 | 100.00 | 78.57 | 78.57 | 81.40 | 81.40 | 81.48 | 81.48 | /workspace/coverage/default/12.prim_esc_test.1970186906 |
| 88.27 | 2.14 | 93.33 | 0.95 | 85.37 | 2.44 | 100.00 | 0.00 | 85.71 | 7.14 | 83.72 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/8.prim_esc_test.3260422817 |
| 89.41 | 1.14 | 94.29 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.05 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/10.prim_esc_test.4017674809 |
| 90.55 | 1.14 | 95.24 | 0.95 | 85.37 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.37 | 2.33 | 81.48 | 0.00 | /workspace/coverage/default/5.prim_esc_test.2576791310 |
| 91.15 | 0.60 | 95.24 | 0.00 | 85.37 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.37 | 0.00 | 81.48 | 0.00 | /workspace/coverage/default/19.prim_esc_test.3547435353 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.375430604 |
| /workspace/coverage/default/1.prim_esc_test.1639735597 |
| /workspace/coverage/default/11.prim_esc_test.2661859515 |
| /workspace/coverage/default/13.prim_esc_test.3092935183 |
| /workspace/coverage/default/14.prim_esc_test.4153568041 |
| /workspace/coverage/default/15.prim_esc_test.2120689266 |
| /workspace/coverage/default/16.prim_esc_test.508574142 |
| /workspace/coverage/default/17.prim_esc_test.3769525929 |
| /workspace/coverage/default/18.prim_esc_test.2596733059 |
| /workspace/coverage/default/2.prim_esc_test.1966616018 |
| /workspace/coverage/default/3.prim_esc_test.2845865226 |
| /workspace/coverage/default/4.prim_esc_test.3477630302 |
| /workspace/coverage/default/6.prim_esc_test.1723137067 |
| /workspace/coverage/default/7.prim_esc_test.445958868 |
| /workspace/coverage/default/9.prim_esc_test.609295782 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/16.prim_esc_test.508574142 | Jul 24 04:20:09 PM PDT 24 | Jul 24 04:20:10 PM PDT 24 | 4557116 ps | ||
| T2 | /workspace/coverage/default/12.prim_esc_test.1970186906 | Jul 24 04:20:13 PM PDT 24 | Jul 24 04:20:13 PM PDT 24 | 5441632 ps | ||
| T3 | /workspace/coverage/default/15.prim_esc_test.2120689266 | Jul 24 04:20:11 PM PDT 24 | Jul 24 04:20:12 PM PDT 24 | 4736487 ps | ||
| T4 | /workspace/coverage/default/10.prim_esc_test.4017674809 | Jul 24 04:20:01 PM PDT 24 | Jul 24 04:20:02 PM PDT 24 | 5010014 ps | ||
| T5 | /workspace/coverage/default/11.prim_esc_test.2661859515 | Jul 24 04:20:12 PM PDT 24 | Jul 24 04:20:13 PM PDT 24 | 4804791 ps | ||
| T13 | /workspace/coverage/default/3.prim_esc_test.2845865226 | Jul 24 04:20:05 PM PDT 24 | Jul 24 04:20:06 PM PDT 24 | 4942206 ps | ||
| T14 | /workspace/coverage/default/0.prim_esc_test.375430604 | Jul 24 04:20:05 PM PDT 24 | Jul 24 04:20:06 PM PDT 24 | 5106373 ps | ||
| T7 | /workspace/coverage/default/17.prim_esc_test.3769525929 | Jul 24 04:20:00 PM PDT 24 | Jul 24 04:20:01 PM PDT 24 | 4878566 ps | ||
| T6 | /workspace/coverage/default/5.prim_esc_test.2576791310 | Jul 24 04:20:05 PM PDT 24 | Jul 24 04:20:06 PM PDT 24 | 4833150 ps | ||
| T15 | /workspace/coverage/default/14.prim_esc_test.4153568041 | Jul 24 04:20:17 PM PDT 24 | Jul 24 04:20:17 PM PDT 24 | 4483386 ps | ||
| T8 | /workspace/coverage/default/4.prim_esc_test.3477630302 | Jul 24 04:20:00 PM PDT 24 | Jul 24 04:20:01 PM PDT 24 | 5288843 ps | ||
| T10 | /workspace/coverage/default/19.prim_esc_test.3547435353 | Jul 24 04:20:11 PM PDT 24 | Jul 24 04:20:12 PM PDT 24 | 4737283 ps | ||
| T16 | /workspace/coverage/default/6.prim_esc_test.1723137067 | Jul 24 04:20:01 PM PDT 24 | Jul 24 04:20:01 PM PDT 24 | 4460393 ps | ||
| T17 | /workspace/coverage/default/9.prim_esc_test.609295782 | Jul 24 04:20:01 PM PDT 24 | Jul 24 04:20:01 PM PDT 24 | 4848368 ps | ||
| T11 | /workspace/coverage/default/8.prim_esc_test.3260422817 | Jul 24 04:20:01 PM PDT 24 | Jul 24 04:20:02 PM PDT 24 | 5466040 ps | ||
| T12 | /workspace/coverage/default/13.prim_esc_test.3092935183 | Jul 24 04:20:01 PM PDT 24 | Jul 24 04:20:02 PM PDT 24 | 5000382 ps | ||
| T9 | /workspace/coverage/default/7.prim_esc_test.445958868 | Jul 24 04:20:05 PM PDT 24 | Jul 24 04:20:06 PM PDT 24 | 4733470 ps | ||
| T18 | /workspace/coverage/default/18.prim_esc_test.2596733059 | Jul 24 04:20:11 PM PDT 24 | Jul 24 04:20:12 PM PDT 24 | 4740874 ps | ||
| T19 | /workspace/coverage/default/1.prim_esc_test.1639735597 | Jul 24 04:20:05 PM PDT 24 | Jul 24 04:20:06 PM PDT 24 | 4352459 ps | ||
| T20 | /workspace/coverage/default/2.prim_esc_test.1966616018 | Jul 24 04:20:00 PM PDT 24 | Jul 24 04:20:01 PM PDT 24 | 4730799 ps |
| Test location | /workspace/coverage/default/12.prim_esc_test.1970186906 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5441632 ps |
| CPU time | 0.39 seconds |
| Started | Jul 24 04:20:13 PM PDT 24 |
| Finished | Jul 24 04:20:13 PM PDT 24 |
| Peak memory | 146284 kb |
| Host | smart-ecb2a1c7-7405-4bfd-8fd2-096d00c31c47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1970186906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1970186906 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3260422817 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5466040 ps |
| CPU time | 0.39 seconds |
| Started | Jul 24 04:20:01 PM PDT 24 |
| Finished | Jul 24 04:20:02 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-b518ddef-54ba-41ca-bbb5-7db4ca9a1167 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3260422817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3260422817 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.4017674809 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5010014 ps |
| CPU time | 0.41 seconds |
| Started | Jul 24 04:20:01 PM PDT 24 |
| Finished | Jul 24 04:20:02 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-6cd288b7-b41e-4e55-bde0-c940c5a664cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017674809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.4017674809 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2576791310 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4833150 ps |
| CPU time | 0.46 seconds |
| Started | Jul 24 04:20:05 PM PDT 24 |
| Finished | Jul 24 04:20:06 PM PDT 24 |
| Peak memory | 143976 kb |
| Host | smart-52e9f70f-fdf3-4a9d-8289-5cd951358161 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2576791310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2576791310 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3547435353 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4737283 ps |
| CPU time | 0.36 seconds |
| Started | Jul 24 04:20:11 PM PDT 24 |
| Finished | Jul 24 04:20:12 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-e901c973-0657-47f4-bf1c-bd8a0ce77e24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3547435353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3547435353 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.375430604 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5106373 ps |
| CPU time | 0.45 seconds |
| Started | Jul 24 04:20:05 PM PDT 24 |
| Finished | Jul 24 04:20:06 PM PDT 24 |
| Peak memory | 143780 kb |
| Host | smart-f9cd4817-c26f-459c-99e2-7edee34b8d4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375430604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.375430604 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.1639735597 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4352459 ps |
| CPU time | 0.48 seconds |
| Started | Jul 24 04:20:05 PM PDT 24 |
| Finished | Jul 24 04:20:06 PM PDT 24 |
| Peak memory | 145820 kb |
| Host | smart-f4f239be-913a-40bd-958c-291da21ea655 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639735597 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1639735597 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2661859515 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4804791 ps |
| CPU time | 0.39 seconds |
| Started | Jul 24 04:20:12 PM PDT 24 |
| Finished | Jul 24 04:20:13 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-75d42b1b-c579-4cee-a8d5-81c78581300b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661859515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2661859515 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3092935183 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5000382 ps |
| CPU time | 0.38 seconds |
| Started | Jul 24 04:20:01 PM PDT 24 |
| Finished | Jul 24 04:20:02 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-019df0f8-c061-4b2c-bedd-b5e3cff45fdc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3092935183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3092935183 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.4153568041 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4483386 ps |
| CPU time | 0.38 seconds |
| Started | Jul 24 04:20:17 PM PDT 24 |
| Finished | Jul 24 04:20:17 PM PDT 24 |
| Peak memory | 146024 kb |
| Host | smart-7b5921ca-dedf-498f-a317-892f58491994 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4153568041 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.4153568041 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.2120689266 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4736487 ps |
| CPU time | 0.4 seconds |
| Started | Jul 24 04:20:11 PM PDT 24 |
| Finished | Jul 24 04:20:12 PM PDT 24 |
| Peak memory | 146196 kb |
| Host | smart-e96379d6-f9cd-4d73-b1d8-31aee7b9a438 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2120689266 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2120689266 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.508574142 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4557116 ps |
| CPU time | 0.42 seconds |
| Started | Jul 24 04:20:09 PM PDT 24 |
| Finished | Jul 24 04:20:10 PM PDT 24 |
| Peak memory | 145036 kb |
| Host | smart-ba7037f6-a192-44ef-8654-92f51e202869 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=508574142 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.508574142 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3769525929 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4878566 ps |
| CPU time | 0.38 seconds |
| Started | Jul 24 04:20:00 PM PDT 24 |
| Finished | Jul 24 04:20:01 PM PDT 24 |
| Peak memory | 145344 kb |
| Host | smart-38175694-4be4-40cc-a375-62081b42433e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3769525929 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3769525929 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2596733059 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4740874 ps |
| CPU time | 0.36 seconds |
| Started | Jul 24 04:20:11 PM PDT 24 |
| Finished | Jul 24 04:20:12 PM PDT 24 |
| Peak memory | 146816 kb |
| Host | smart-049a35f7-d70e-493a-893e-da94b542c53e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596733059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2596733059 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1966616018 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4730799 ps |
| CPU time | 0.38 seconds |
| Started | Jul 24 04:20:00 PM PDT 24 |
| Finished | Jul 24 04:20:01 PM PDT 24 |
| Peak memory | 145228 kb |
| Host | smart-c64159ff-70ce-4d51-8480-f48736075294 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1966616018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1966616018 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2845865226 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4942206 ps |
| CPU time | 0.47 seconds |
| Started | Jul 24 04:20:05 PM PDT 24 |
| Finished | Jul 24 04:20:06 PM PDT 24 |
| Peak memory | 144856 kb |
| Host | smart-09e4035a-76e9-46e8-a46b-b5c1b057e962 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2845865226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2845865226 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3477630302 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5288843 ps |
| CPU time | 0.4 seconds |
| Started | Jul 24 04:20:00 PM PDT 24 |
| Finished | Jul 24 04:20:01 PM PDT 24 |
| Peak memory | 144256 kb |
| Host | smart-ac0a0164-9f6b-4c1d-b92f-a559ed7f252e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3477630302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3477630302 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1723137067 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4460393 ps |
| CPU time | 0.38 seconds |
| Started | Jul 24 04:20:01 PM PDT 24 |
| Finished | Jul 24 04:20:01 PM PDT 24 |
| Peak memory | 145180 kb |
| Host | smart-0287ed20-30e8-4290-a3c9-adb868a8a1e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1723137067 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1723137067 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.445958868 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4733470 ps |
| CPU time | 0.45 seconds |
| Started | Jul 24 04:20:05 PM PDT 24 |
| Finished | Jul 24 04:20:06 PM PDT 24 |
| Peak memory | 144736 kb |
| Host | smart-9996f7f0-12df-4dd2-8776-782a35e34eb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=445958868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.445958868 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.609295782 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4848368 ps |
| CPU time | 0.36 seconds |
| Started | Jul 24 04:20:01 PM PDT 24 |
| Finished | Jul 24 04:20:01 PM PDT 24 |
| Peak memory | 146760 kb |
| Host | smart-ab1efd28-67f1-4271-a417-3f805fd12868 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=609295782 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.609295782 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |