| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.17 | 94.50 | 87.80 | 100.00 | 92.86 | 86.67 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.14 | 86.14 | 92.66 | 92.66 | 85.37 | 85.37 | 100.00 | 100.00 | 71.43 | 71.43 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/4.prim_esc_test.1454073810 |
| 89.45 | 3.31 | 93.58 | 0.92 | 87.80 | 2.44 | 100.00 | 0.00 | 85.71 | 14.29 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/15.prim_esc_test.1215599233 |
| 91.17 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/19.prim_esc_test.3695570123 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1607643254 |
| /workspace/coverage/default/1.prim_esc_test.2626404066 |
| /workspace/coverage/default/10.prim_esc_test.30907687 |
| /workspace/coverage/default/11.prim_esc_test.4199771018 |
| /workspace/coverage/default/12.prim_esc_test.448279155 |
| /workspace/coverage/default/13.prim_esc_test.46180789 |
| /workspace/coverage/default/14.prim_esc_test.1114158367 |
| /workspace/coverage/default/16.prim_esc_test.3993367569 |
| /workspace/coverage/default/17.prim_esc_test.2631373969 |
| /workspace/coverage/default/18.prim_esc_test.3548561279 |
| /workspace/coverage/default/2.prim_esc_test.3073090354 |
| /workspace/coverage/default/3.prim_esc_test.1126041781 |
| /workspace/coverage/default/5.prim_esc_test.2607455806 |
| /workspace/coverage/default/6.prim_esc_test.1404781459 |
| /workspace/coverage/default/7.prim_esc_test.1053832175 |
| /workspace/coverage/default/8.prim_esc_test.3768407534 |
| /workspace/coverage/default/9.prim_esc_test.2352360507 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/0.prim_esc_test.1607643254 | Jul 25 04:19:25 PM PDT 24 | Jul 25 04:19:25 PM PDT 24 | 4651448 ps | ||
| T2 | /workspace/coverage/default/7.prim_esc_test.1053832175 | Jul 25 04:19:24 PM PDT 24 | Jul 25 04:19:25 PM PDT 24 | 4717714 ps | ||
| T3 | /workspace/coverage/default/9.prim_esc_test.2352360507 | Jul 25 04:19:18 PM PDT 24 | Jul 25 04:19:19 PM PDT 24 | 5222631 ps | ||
| T4 | /workspace/coverage/default/2.prim_esc_test.3073090354 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:19:27 PM PDT 24 | 4823968 ps | ||
| T5 | /workspace/coverage/default/19.prim_esc_test.3695570123 | Jul 25 04:19:27 PM PDT 24 | Jul 25 04:19:28 PM PDT 24 | 5255285 ps | ||
| T6 | /workspace/coverage/default/4.prim_esc_test.1454073810 | Jul 25 04:19:18 PM PDT 24 | Jul 25 04:19:19 PM PDT 24 | 5073911 ps | ||
| T13 | /workspace/coverage/default/5.prim_esc_test.2607455806 | Jul 25 04:19:24 PM PDT 24 | Jul 25 04:19:25 PM PDT 24 | 4537098 ps | ||
| T12 | /workspace/coverage/default/18.prim_esc_test.3548561279 | Jul 25 04:19:25 PM PDT 24 | Jul 25 04:19:26 PM PDT 24 | 4614788 ps | ||
| T14 | /workspace/coverage/default/16.prim_esc_test.3993367569 | Jul 25 04:19:28 PM PDT 24 | Jul 25 04:19:29 PM PDT 24 | 4796581 ps | ||
| T10 | /workspace/coverage/default/8.prim_esc_test.3768407534 | Jul 25 04:19:26 PM PDT 24 | Jul 25 04:19:26 PM PDT 24 | 5079620 ps | ||
| T15 | /workspace/coverage/default/10.prim_esc_test.30907687 | Jul 25 04:19:26 PM PDT 24 | Jul 25 04:19:26 PM PDT 24 | 4574651 ps | ||
| T7 | /workspace/coverage/default/15.prim_esc_test.1215599233 | Jul 25 04:19:25 PM PDT 24 | Jul 25 04:19:26 PM PDT 24 | 4296025 ps | ||
| T8 | /workspace/coverage/default/6.prim_esc_test.1404781459 | Jul 25 04:19:26 PM PDT 24 | Jul 25 04:19:26 PM PDT 24 | 4829870 ps | ||
| T16 | /workspace/coverage/default/14.prim_esc_test.1114158367 | Jul 25 04:19:26 PM PDT 24 | Jul 25 04:19:26 PM PDT 24 | 5109534 ps | ||
| T17 | /workspace/coverage/default/3.prim_esc_test.1126041781 | Jul 25 04:20:07 PM PDT 24 | Jul 25 04:20:08 PM PDT 24 | 4773638 ps | ||
| T11 | /workspace/coverage/default/13.prim_esc_test.46180789 | Jul 25 04:19:29 PM PDT 24 | Jul 25 04:19:30 PM PDT 24 | 4385619 ps | ||
| T18 | /workspace/coverage/default/11.prim_esc_test.4199771018 | Jul 25 04:19:26 PM PDT 24 | Jul 25 04:19:27 PM PDT 24 | 4889971 ps | ||
| T19 | /workspace/coverage/default/17.prim_esc_test.2631373969 | Jul 25 04:19:18 PM PDT 24 | Jul 25 04:19:19 PM PDT 24 | 4930502 ps | ||
| T9 | /workspace/coverage/default/12.prim_esc_test.448279155 | Jul 25 04:19:24 PM PDT 24 | Jul 25 04:19:25 PM PDT 24 | 5419078 ps | ||
| T20 | /workspace/coverage/default/1.prim_esc_test.2626404066 | Jul 25 04:19:29 PM PDT 24 | Jul 25 04:19:29 PM PDT 24 | 4778853 ps |
| Test location | /workspace/coverage/default/4.prim_esc_test.1454073810 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5073911 ps |
| CPU time | 0.45 seconds |
| Started | Jul 25 04:19:18 PM PDT 24 |
| Finished | Jul 25 04:19:19 PM PDT 24 |
| Peak memory | 145500 kb |
| Host | smart-90dddfe5-5226-4548-939a-e4b836d1b28c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1454073810 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1454073810 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1215599233 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4296025 ps |
| CPU time | 0.4 seconds |
| Started | Jul 25 04:19:25 PM PDT 24 |
| Finished | Jul 25 04:19:26 PM PDT 24 |
| Peak memory | 145668 kb |
| Host | smart-4dd4ec94-a6e4-4020-bafd-b40a5e060112 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215599233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1215599233 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3695570123 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5255285 ps |
| CPU time | 0.41 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:19:28 PM PDT 24 |
| Peak memory | 146736 kb |
| Host | smart-97d91f8f-895f-45e3-ac16-a8056f4638f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3695570123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3695570123 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1607643254 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4651448 ps |
| CPU time | 0.38 seconds |
| Started | Jul 25 04:19:25 PM PDT 24 |
| Finished | Jul 25 04:19:25 PM PDT 24 |
| Peak memory | 146456 kb |
| Host | smart-a7347676-7ff9-44b7-be09-2ed3331df6fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1607643254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1607643254 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2626404066 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4778853 ps |
| CPU time | 0.39 seconds |
| Started | Jul 25 04:19:29 PM PDT 24 |
| Finished | Jul 25 04:19:29 PM PDT 24 |
| Peak memory | 146140 kb |
| Host | smart-75873d33-0cd0-46a4-95e2-1c0bedf31612 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626404066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2626404066 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.30907687 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4574651 ps |
| CPU time | 0.38 seconds |
| Started | Jul 25 04:19:26 PM PDT 24 |
| Finished | Jul 25 04:19:26 PM PDT 24 |
| Peak memory | 145980 kb |
| Host | smart-ddc331ca-04d9-4a16-be58-381a9feb15a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=30907687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.30907687 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.4199771018 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4889971 ps |
| CPU time | 0.47 seconds |
| Started | Jul 25 04:19:26 PM PDT 24 |
| Finished | Jul 25 04:19:27 PM PDT 24 |
| Peak memory | 146572 kb |
| Host | smart-e617f292-e663-4b37-a318-9c5a1e4d1da0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4199771018 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.4199771018 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.448279155 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5419078 ps |
| CPU time | 0.45 seconds |
| Started | Jul 25 04:19:24 PM PDT 24 |
| Finished | Jul 25 04:19:25 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-e1794968-574e-4c7e-9b0c-483b3e558c51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=448279155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.448279155 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.46180789 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4385619 ps |
| CPU time | 0.36 seconds |
| Started | Jul 25 04:19:29 PM PDT 24 |
| Finished | Jul 25 04:19:30 PM PDT 24 |
| Peak memory | 147132 kb |
| Host | smart-05278e10-a4c5-46e9-ac47-bc8fc21bda37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=46180789 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.46180789 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1114158367 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5109534 ps |
| CPU time | 0.41 seconds |
| Started | Jul 25 04:19:26 PM PDT 24 |
| Finished | Jul 25 04:19:26 PM PDT 24 |
| Peak memory | 145512 kb |
| Host | smart-2998ceae-367c-440a-8b49-ddccd63401d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114158367 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1114158367 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3993367569 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4796581 ps |
| CPU time | 0.36 seconds |
| Started | Jul 25 04:19:28 PM PDT 24 |
| Finished | Jul 25 04:19:29 PM PDT 24 |
| Peak memory | 147228 kb |
| Host | smart-22790168-29f1-4b02-89e2-bb545e213e04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993367569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3993367569 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2631373969 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4930502 ps |
| CPU time | 0.38 seconds |
| Started | Jul 25 04:19:18 PM PDT 24 |
| Finished | Jul 25 04:19:19 PM PDT 24 |
| Peak memory | 145856 kb |
| Host | smart-b1e11155-2711-4d88-b89f-d52ef697e03b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2631373969 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2631373969 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3548561279 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4614788 ps |
| CPU time | 0.37 seconds |
| Started | Jul 25 04:19:25 PM PDT 24 |
| Finished | Jul 25 04:19:26 PM PDT 24 |
| Peak memory | 145888 kb |
| Host | smart-7d129f7a-1148-4a71-b633-85daf4ff30c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3548561279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3548561279 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3073090354 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4823968 ps |
| CPU time | 0.39 seconds |
| Started | Jul 25 04:19:27 PM PDT 24 |
| Finished | Jul 25 04:19:27 PM PDT 24 |
| Peak memory | 146036 kb |
| Host | smart-d8cd3c9d-dcf0-4414-a86a-123a1b251dd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3073090354 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3073090354 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1126041781 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4773638 ps |
| CPU time | 0.39 seconds |
| Started | Jul 25 04:20:07 PM PDT 24 |
| Finished | Jul 25 04:20:08 PM PDT 24 |
| Peak memory | 146588 kb |
| Host | smart-f069b920-d4a0-4fdd-9916-e15687057194 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1126041781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1126041781 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2607455806 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4537098 ps |
| CPU time | 0.44 seconds |
| Started | Jul 25 04:19:24 PM PDT 24 |
| Finished | Jul 25 04:19:25 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-399b3aba-7efd-4686-b2db-7e74a93c1829 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607455806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2607455806 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1404781459 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4829870 ps |
| CPU time | 0.4 seconds |
| Started | Jul 25 04:19:26 PM PDT 24 |
| Finished | Jul 25 04:19:26 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-0256dfab-70c5-4a43-a597-e2c55c0dd857 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1404781459 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1404781459 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1053832175 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4717714 ps |
| CPU time | 0.41 seconds |
| Started | Jul 25 04:19:24 PM PDT 24 |
| Finished | Jul 25 04:19:25 PM PDT 24 |
| Peak memory | 144976 kb |
| Host | smart-ea3f236a-06a7-4eee-96bd-0824928c40d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053832175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1053832175 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3768407534 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5079620 ps |
| CPU time | 0.37 seconds |
| Started | Jul 25 04:19:26 PM PDT 24 |
| Finished | Jul 25 04:19:26 PM PDT 24 |
| Peak memory | 147148 kb |
| Host | smart-db1c8f41-aab5-43c3-9263-62614a91de61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3768407534 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3768407534 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2352360507 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5222631 ps |
| CPU time | 0.41 seconds |
| Started | Jul 25 04:19:18 PM PDT 24 |
| Finished | Jul 25 04:19:19 PM PDT 24 |
| Peak memory | 145732 kb |
| Host | smart-ae60539e-9d73-41cf-8bf1-787fbebb704d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2352360507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2352360507 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |