| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/8.prim_esc_test.2714891670 |
| 89.45 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/17.prim_esc_test.2781915954 |
| 90.57 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/10.prim_esc_test.3540766556 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/16.prim_esc_test.2266721918 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspace/coverage/default/11.prim_esc_test.2990960340 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.302036981 |
| /workspace/coverage/default/1.prim_esc_test.2969107786 |
| /workspace/coverage/default/12.prim_esc_test.3399080566 |
| /workspace/coverage/default/13.prim_esc_test.2278813834 |
| /workspace/coverage/default/14.prim_esc_test.495761351 |
| /workspace/coverage/default/15.prim_esc_test.692111462 |
| /workspace/coverage/default/18.prim_esc_test.3306376470 |
| /workspace/coverage/default/19.prim_esc_test.2148392967 |
| /workspace/coverage/default/2.prim_esc_test.3008587640 |
| /workspace/coverage/default/3.prim_esc_test.387815062 |
| /workspace/coverage/default/4.prim_esc_test.72387742 |
| /workspace/coverage/default/5.prim_esc_test.2314186994 |
| /workspace/coverage/default/6.prim_esc_test.4073386631 |
| /workspace/coverage/default/7.prim_esc_test.4263695012 |
| /workspace/coverage/default/9.prim_esc_test.4107774476 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/19.prim_esc_test.2148392967 | Jul 26 04:25:10 PM PDT 24 | Jul 26 04:25:11 PM PDT 24 | 4894447 ps | ||
| T2 | /workspace/coverage/default/14.prim_esc_test.495761351 | Jul 26 04:19:52 PM PDT 24 | Jul 26 04:19:52 PM PDT 24 | 4761680 ps | ||
| T3 | /workspace/coverage/default/8.prim_esc_test.2714891670 | Jul 26 04:20:55 PM PDT 24 | Jul 26 04:20:56 PM PDT 24 | 4608510 ps | ||
| T5 | /workspace/coverage/default/3.prim_esc_test.387815062 | Jul 26 04:21:11 PM PDT 24 | Jul 26 04:21:12 PM PDT 24 | 5382826 ps | ||
| T12 | /workspace/coverage/default/17.prim_esc_test.2781915954 | Jul 26 04:19:53 PM PDT 24 | Jul 26 04:19:53 PM PDT 24 | 5018578 ps | ||
| T14 | /workspace/coverage/default/0.prim_esc_test.302036981 | Jul 26 04:19:53 PM PDT 24 | Jul 26 04:19:54 PM PDT 24 | 5150450 ps | ||
| T6 | /workspace/coverage/default/6.prim_esc_test.4073386631 | Jul 26 04:19:54 PM PDT 24 | Jul 26 04:19:55 PM PDT 24 | 5076444 ps | ||
| T9 | /workspace/coverage/default/18.prim_esc_test.3306376470 | Jul 26 04:19:56 PM PDT 24 | Jul 26 04:19:56 PM PDT 24 | 4957673 ps | ||
| T4 | /workspace/coverage/default/2.prim_esc_test.3008587640 | Jul 26 04:19:43 PM PDT 24 | Jul 26 04:19:44 PM PDT 24 | 4906761 ps | ||
| T15 | /workspace/coverage/default/7.prim_esc_test.4263695012 | Jul 26 04:19:52 PM PDT 24 | Jul 26 04:19:53 PM PDT 24 | 4498802 ps | ||
| T7 | /workspace/coverage/default/11.prim_esc_test.2990960340 | Jul 26 04:19:54 PM PDT 24 | Jul 26 04:19:54 PM PDT 24 | 4405587 ps | ||
| T11 | /workspace/coverage/default/4.prim_esc_test.72387742 | Jul 26 04:19:56 PM PDT 24 | Jul 26 04:19:57 PM PDT 24 | 5045566 ps | ||
| T16 | /workspace/coverage/default/5.prim_esc_test.2314186994 | Jul 26 04:20:54 PM PDT 24 | Jul 26 04:20:55 PM PDT 24 | 4882288 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.3540766556 | Jul 26 04:19:42 PM PDT 24 | Jul 26 04:19:44 PM PDT 24 | 4694236 ps | ||
| T17 | /workspace/coverage/default/9.prim_esc_test.4107774476 | Jul 26 04:19:52 PM PDT 24 | Jul 26 04:19:53 PM PDT 24 | 4701065 ps | ||
| T18 | /workspace/coverage/default/16.prim_esc_test.2266721918 | Jul 26 04:19:42 PM PDT 24 | Jul 26 04:19:43 PM PDT 24 | 5022817 ps | ||
| T13 | /workspace/coverage/default/15.prim_esc_test.692111462 | Jul 26 04:19:54 PM PDT 24 | Jul 26 04:19:55 PM PDT 24 | 4882287 ps | ||
| T8 | /workspace/coverage/default/12.prim_esc_test.3399080566 | Jul 26 04:26:02 PM PDT 24 | Jul 26 04:26:02 PM PDT 24 | 4847126 ps | ||
| T19 | /workspace/coverage/default/13.prim_esc_test.2278813834 | Jul 26 04:19:53 PM PDT 24 | Jul 26 04:19:54 PM PDT 24 | 5089474 ps | ||
| T20 | /workspace/coverage/default/1.prim_esc_test.2969107786 | Jul 26 04:19:54 PM PDT 24 | Jul 26 04:19:55 PM PDT 24 | 4683951 ps |
| Test location | /workspace/coverage/default/8.prim_esc_test.2714891670 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4608510 ps |
| CPU time | 0.37 seconds |
| Started | Jul 26 04:20:55 PM PDT 24 |
| Finished | Jul 26 04:20:56 PM PDT 24 |
| Peak memory | 146268 kb |
| Host | smart-f74d58db-8ad9-4d61-b4de-9e75da774051 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714891670 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2714891670 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2781915954 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5018578 ps |
| CPU time | 0.38 seconds |
| Started | Jul 26 04:19:53 PM PDT 24 |
| Finished | Jul 26 04:19:53 PM PDT 24 |
| Peak memory | 146132 kb |
| Host | smart-234adf77-9315-4079-9959-75fff96ee5c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2781915954 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2781915954 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3540766556 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4694236 ps |
| CPU time | 0.44 seconds |
| Started | Jul 26 04:19:42 PM PDT 24 |
| Finished | Jul 26 04:19:44 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-999b972b-3e68-4051-9c0f-ae1a84af613b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3540766556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3540766556 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2266721918 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5022817 ps |
| CPU time | 0.38 seconds |
| Started | Jul 26 04:19:42 PM PDT 24 |
| Finished | Jul 26 04:19:43 PM PDT 24 |
| Peak memory | 146680 kb |
| Host | smart-383b5193-c8b2-4909-9709-f6f63a9f561c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266721918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2266721918 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2990960340 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4405587 ps |
| CPU time | 0.38 seconds |
| Started | Jul 26 04:19:54 PM PDT 24 |
| Finished | Jul 26 04:19:54 PM PDT 24 |
| Peak memory | 146140 kb |
| Host | smart-98ed2a5e-a053-4df5-a8ab-818d9e150fa4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2990960340 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2990960340 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.302036981 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5150450 ps |
| CPU time | 0.41 seconds |
| Started | Jul 26 04:19:53 PM PDT 24 |
| Finished | Jul 26 04:19:54 PM PDT 24 |
| Peak memory | 146692 kb |
| Host | smart-22bc8159-743a-4061-b13a-c4c9992bf6d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=302036981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.302036981 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2969107786 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4683951 ps |
| CPU time | 0.36 seconds |
| Started | Jul 26 04:19:54 PM PDT 24 |
| Finished | Jul 26 04:19:55 PM PDT 24 |
| Peak memory | 146204 kb |
| Host | smart-0c2b2df8-6494-448d-a9cd-f5e4ee291db8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969107786 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2969107786 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3399080566 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4847126 ps |
| CPU time | 0.38 seconds |
| Started | Jul 26 04:26:02 PM PDT 24 |
| Finished | Jul 26 04:26:02 PM PDT 24 |
| Peak memory | 146112 kb |
| Host | smart-382d515f-af78-4780-aded-ba015e549228 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3399080566 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3399080566 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2278813834 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5089474 ps |
| CPU time | 0.39 seconds |
| Started | Jul 26 04:19:53 PM PDT 24 |
| Finished | Jul 26 04:19:54 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-0ceb4a90-3e7a-4bd1-8af5-26b2e72e0c4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2278813834 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2278813834 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.495761351 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4761680 ps |
| CPU time | 0.4 seconds |
| Started | Jul 26 04:19:52 PM PDT 24 |
| Finished | Jul 26 04:19:52 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-5be70926-1430-4357-aab5-dcae1ad24f21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495761351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.495761351 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.692111462 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4882287 ps |
| CPU time | 0.39 seconds |
| Started | Jul 26 04:19:54 PM PDT 24 |
| Finished | Jul 26 04:19:55 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-017db5fa-1d86-434a-93fe-891a9f2e2da8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=692111462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.692111462 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3306376470 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4957673 ps |
| CPU time | 0.39 seconds |
| Started | Jul 26 04:19:56 PM PDT 24 |
| Finished | Jul 26 04:19:56 PM PDT 24 |
| Peak memory | 146612 kb |
| Host | smart-e15a007f-f87c-48ee-a405-3f3d38f680e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3306376470 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3306376470 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2148392967 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4894447 ps |
| CPU time | 0.44 seconds |
| Started | Jul 26 04:25:10 PM PDT 24 |
| Finished | Jul 26 04:25:11 PM PDT 24 |
| Peak memory | 146348 kb |
| Host | smart-2bce4d95-9104-4f99-a780-3fd64f30cf1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148392967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2148392967 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3008587640 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4906761 ps |
| CPU time | 0.46 seconds |
| Started | Jul 26 04:19:43 PM PDT 24 |
| Finished | Jul 26 04:19:44 PM PDT 24 |
| Peak memory | 145200 kb |
| Host | smart-c23d535b-c5cc-4214-aa25-a3512e7e90f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008587640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3008587640 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.387815062 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5382826 ps |
| CPU time | 0.39 seconds |
| Started | Jul 26 04:21:11 PM PDT 24 |
| Finished | Jul 26 04:21:12 PM PDT 24 |
| Peak memory | 146364 kb |
| Host | smart-cd8d32be-59bf-475d-b1e4-1b6c7247df33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387815062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.387815062 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.72387742 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5045566 ps |
| CPU time | 0.37 seconds |
| Started | Jul 26 04:19:56 PM PDT 24 |
| Finished | Jul 26 04:19:57 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-62374b26-c6a0-4623-8526-8afd099270bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72387742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.72387742 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2314186994 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4882288 ps |
| CPU time | 0.38 seconds |
| Started | Jul 26 04:20:54 PM PDT 24 |
| Finished | Jul 26 04:20:55 PM PDT 24 |
| Peak memory | 145444 kb |
| Host | smart-adb5751c-cf84-4b38-ad90-4a15660aa0aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314186994 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2314186994 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.4073386631 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5076444 ps |
| CPU time | 0.42 seconds |
| Started | Jul 26 04:19:54 PM PDT 24 |
| Finished | Jul 26 04:19:55 PM PDT 24 |
| Peak memory | 146204 kb |
| Host | smart-a64d0fd4-958a-4f0c-9040-e170b4776843 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4073386631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4073386631 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.4263695012 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4498802 ps |
| CPU time | 0.38 seconds |
| Started | Jul 26 04:19:52 PM PDT 24 |
| Finished | Jul 26 04:19:53 PM PDT 24 |
| Peak memory | 145948 kb |
| Host | smart-fbf0d5c2-3c7e-45c1-9176-61049b7ef537 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4263695012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.4263695012 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.4107774476 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4701065 ps |
| CPU time | 0.39 seconds |
| Started | Jul 26 04:19:52 PM PDT 24 |
| Finished | Jul 26 04:19:53 PM PDT 24 |
| Peak memory | 145564 kb |
| Host | smart-d18b1452-f9b3-4848-84f9-2ba76d4d5afa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4107774476 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.4107774476 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |