| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/18.prim_esc_test.2054057827 |
| 89.45 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/8.prim_esc_test.1854377814 |
| 90.57 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/10.prim_esc_test.1789111850 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/13.prim_esc_test.426311106 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspace/coverage/default/0.prim_esc_test.722866021 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.2013287912 |
| /workspace/coverage/default/11.prim_esc_test.4040063578 |
| /workspace/coverage/default/12.prim_esc_test.2039655401 |
| /workspace/coverage/default/14.prim_esc_test.2605765403 |
| /workspace/coverage/default/15.prim_esc_test.4055709806 |
| /workspace/coverage/default/16.prim_esc_test.3583786369 |
| /workspace/coverage/default/17.prim_esc_test.2917373341 |
| /workspace/coverage/default/19.prim_esc_test.191212556 |
| /workspace/coverage/default/2.prim_esc_test.67433471 |
| /workspace/coverage/default/3.prim_esc_test.1523979845 |
| /workspace/coverage/default/4.prim_esc_test.1683507485 |
| /workspace/coverage/default/5.prim_esc_test.2581910796 |
| /workspace/coverage/default/6.prim_esc_test.2767227284 |
| /workspace/coverage/default/7.prim_esc_test.2129843783 |
| /workspace/coverage/default/9.prim_esc_test.1580303138 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/1.prim_esc_test.2013287912 | Jul 27 04:22:07 PM PDT 24 | Jul 27 04:22:08 PM PDT 24 | 4825932 ps | ||
| T2 | /workspace/coverage/default/7.prim_esc_test.2129843783 | Jul 27 04:17:34 PM PDT 24 | Jul 27 04:17:34 PM PDT 24 | 4996273 ps | ||
| T3 | /workspace/coverage/default/2.prim_esc_test.67433471 | Jul 27 04:17:35 PM PDT 24 | Jul 27 04:17:36 PM PDT 24 | 4551919 ps | ||
| T4 | /workspace/coverage/default/13.prim_esc_test.426311106 | Jul 27 04:22:06 PM PDT 24 | Jul 27 04:22:07 PM PDT 24 | 5259022 ps | ||
| T6 | /workspace/coverage/default/3.prim_esc_test.1523979845 | Jul 27 04:17:47 PM PDT 24 | Jul 27 04:17:48 PM PDT 24 | 4358760 ps | ||
| T16 | /workspace/coverage/default/16.prim_esc_test.3583786369 | Jul 27 04:23:15 PM PDT 24 | Jul 27 04:23:16 PM PDT 24 | 4636701 ps | ||
| T5 | /workspace/coverage/default/18.prim_esc_test.2054057827 | Jul 27 04:17:36 PM PDT 24 | Jul 27 04:17:37 PM PDT 24 | 4290495 ps | ||
| T9 | /workspace/coverage/default/8.prim_esc_test.1854377814 | Jul 27 04:23:15 PM PDT 24 | Jul 27 04:23:15 PM PDT 24 | 4604914 ps | ||
| T10 | /workspace/coverage/default/15.prim_esc_test.4055709806 | Jul 27 04:17:29 PM PDT 24 | Jul 27 04:17:29 PM PDT 24 | 4783662 ps | ||
| T13 | /workspace/coverage/default/12.prim_esc_test.2039655401 | Jul 27 04:18:41 PM PDT 24 | Jul 27 04:18:41 PM PDT 24 | 5044589 ps | ||
| T11 | /workspace/coverage/default/6.prim_esc_test.2767227284 | Jul 27 04:17:35 PM PDT 24 | Jul 27 04:17:36 PM PDT 24 | 5752920 ps | ||
| T14 | /workspace/coverage/default/4.prim_esc_test.1683507485 | Jul 27 04:18:47 PM PDT 24 | Jul 27 04:18:48 PM PDT 24 | 4271310 ps | ||
| T17 | /workspace/coverage/default/11.prim_esc_test.4040063578 | Jul 27 04:17:40 PM PDT 24 | Jul 27 04:17:40 PM PDT 24 | 5152199 ps | ||
| T8 | /workspace/coverage/default/17.prim_esc_test.2917373341 | Jul 27 04:20:53 PM PDT 24 | Jul 27 04:20:54 PM PDT 24 | 4637982 ps | ||
| T18 | /workspace/coverage/default/14.prim_esc_test.2605765403 | Jul 27 04:17:40 PM PDT 24 | Jul 27 04:17:40 PM PDT 24 | 4491402 ps | ||
| T7 | /workspace/coverage/default/5.prim_esc_test.2581910796 | Jul 27 04:22:01 PM PDT 24 | Jul 27 04:22:02 PM PDT 24 | 4382989 ps | ||
| T15 | /workspace/coverage/default/9.prim_esc_test.1580303138 | Jul 27 04:17:34 PM PDT 24 | Jul 27 04:17:35 PM PDT 24 | 4518040 ps | ||
| T19 | /workspace/coverage/default/19.prim_esc_test.191212556 | Jul 27 04:18:10 PM PDT 24 | Jul 27 04:18:10 PM PDT 24 | 4684662 ps | ||
| T20 | /workspace/coverage/default/10.prim_esc_test.1789111850 | Jul 27 04:17:33 PM PDT 24 | Jul 27 04:17:34 PM PDT 24 | 4857569 ps | ||
| T12 | /workspace/coverage/default/0.prim_esc_test.722866021 | Jul 27 04:17:38 PM PDT 24 | Jul 27 04:17:38 PM PDT 24 | 4859717 ps |
| Test location | /workspace/coverage/default/18.prim_esc_test.2054057827 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4290495 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 04:17:36 PM PDT 24 |
| Finished | Jul 27 04:17:37 PM PDT 24 |
| Peak memory | 145344 kb |
| Host | smart-728fd189-c62c-49f9-a12c-15932eccffd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054057827 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2054057827 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1854377814 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4604914 ps |
| CPU time | 0.45 seconds |
| Started | Jul 27 04:23:15 PM PDT 24 |
| Finished | Jul 27 04:23:15 PM PDT 24 |
| Peak memory | 146132 kb |
| Host | smart-5fc688f9-2927-4941-b8cd-05b2d895158c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1854377814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1854377814 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1789111850 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4857569 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 04:17:33 PM PDT 24 |
| Finished | Jul 27 04:17:34 PM PDT 24 |
| Peak memory | 145536 kb |
| Host | smart-624c12b1-d587-45c1-8f60-49dec0b38d07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1789111850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1789111850 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.426311106 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5259022 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 04:22:06 PM PDT 24 |
| Finished | Jul 27 04:22:07 PM PDT 24 |
| Peak memory | 145064 kb |
| Host | smart-184d9cba-9c93-4c90-a6a4-61b29e438aa3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=426311106 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.426311106 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.722866021 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4859717 ps |
| CPU time | 0.37 seconds |
| Started | Jul 27 04:17:38 PM PDT 24 |
| Finished | Jul 27 04:17:38 PM PDT 24 |
| Peak memory | 146364 kb |
| Host | smart-797acbe5-54a4-4afc-b98b-ecb024d2b3a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=722866021 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.722866021 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2013287912 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4825932 ps |
| CPU time | 0.41 seconds |
| Started | Jul 27 04:22:07 PM PDT 24 |
| Finished | Jul 27 04:22:08 PM PDT 24 |
| Peak memory | 144792 kb |
| Host | smart-d6c4c1a8-7050-4ab3-b1b8-97c8baab58ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2013287912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2013287912 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.4040063578 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5152199 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 04:17:40 PM PDT 24 |
| Finished | Jul 27 04:17:40 PM PDT 24 |
| Peak memory | 145636 kb |
| Host | smart-da992149-cbb2-4a7b-a6b4-95c84419a685 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040063578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.4040063578 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2039655401 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5044589 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 04:18:41 PM PDT 24 |
| Finished | Jul 27 04:18:41 PM PDT 24 |
| Peak memory | 145824 kb |
| Host | smart-0454dde9-4542-47da-830c-cbf3c4197bbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2039655401 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2039655401 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2605765403 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4491402 ps |
| CPU time | 0.39 seconds |
| Started | Jul 27 04:17:40 PM PDT 24 |
| Finished | Jul 27 04:17:40 PM PDT 24 |
| Peak memory | 145972 kb |
| Host | smart-1412adb6-0a32-4498-a1ea-b7e6a8a4ede0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605765403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2605765403 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.4055709806 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4783662 ps |
| CPU time | 0.42 seconds |
| Started | Jul 27 04:17:29 PM PDT 24 |
| Finished | Jul 27 04:17:29 PM PDT 24 |
| Peak memory | 146724 kb |
| Host | smart-3d3a54a3-e521-4c55-bc21-883169c29616 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055709806 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.4055709806 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3583786369 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4636701 ps |
| CPU time | 0.37 seconds |
| Started | Jul 27 04:23:15 PM PDT 24 |
| Finished | Jul 27 04:23:16 PM PDT 24 |
| Peak memory | 146168 kb |
| Host | smart-e6244983-78d7-408d-90e6-55a32fed9aaf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3583786369 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3583786369 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2917373341 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4637982 ps |
| CPU time | 0.4 seconds |
| Started | Jul 27 04:20:53 PM PDT 24 |
| Finished | Jul 27 04:20:54 PM PDT 24 |
| Peak memory | 146228 kb |
| Host | smart-3adad3cb-8242-42d2-981c-5b9b8b2eed9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2917373341 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2917373341 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.191212556 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4684662 ps |
| CPU time | 0.37 seconds |
| Started | Jul 27 04:18:10 PM PDT 24 |
| Finished | Jul 27 04:18:10 PM PDT 24 |
| Peak memory | 146336 kb |
| Host | smart-0a24d8ca-d5da-4699-9ef7-c682cd921aa5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191212556 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.191212556 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.67433471 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4551919 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 04:17:35 PM PDT 24 |
| Finished | Jul 27 04:17:36 PM PDT 24 |
| Peak memory | 146252 kb |
| Host | smart-3238566d-4d97-4df9-8bb8-f44164cbcb01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67433471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.67433471 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1523979845 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4358760 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 04:17:47 PM PDT 24 |
| Finished | Jul 27 04:17:48 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-22dca5f8-182a-477c-83f4-03489251a171 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1523979845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1523979845 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1683507485 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4271310 ps |
| CPU time | 0.37 seconds |
| Started | Jul 27 04:18:47 PM PDT 24 |
| Finished | Jul 27 04:18:48 PM PDT 24 |
| Peak memory | 147196 kb |
| Host | smart-1ddc52fb-c157-4f1b-8c45-03c3c8462b42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1683507485 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1683507485 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2581910796 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4382989 ps |
| CPU time | 0.46 seconds |
| Started | Jul 27 04:22:01 PM PDT 24 |
| Finished | Jul 27 04:22:02 PM PDT 24 |
| Peak memory | 145700 kb |
| Host | smart-9fb338ce-3a96-4377-a00d-033c4f8c3668 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2581910796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2581910796 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2767227284 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5752920 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 04:17:35 PM PDT 24 |
| Finished | Jul 27 04:17:36 PM PDT 24 |
| Peak memory | 146092 kb |
| Host | smart-00bd38a9-a834-42cb-91b0-b0e3c99117ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2767227284 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2767227284 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.2129843783 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4996273 ps |
| CPU time | 0.38 seconds |
| Started | Jul 27 04:17:34 PM PDT 24 |
| Finished | Jul 27 04:17:34 PM PDT 24 |
| Peak memory | 146052 kb |
| Host | smart-349bdf2c-1e49-49d7-bd3d-ce6f9ac2950a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2129843783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2129843783 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1580303138 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4518040 ps |
| CPU time | 0.36 seconds |
| Started | Jul 27 04:17:34 PM PDT 24 |
| Finished | Jul 27 04:17:35 PM PDT 24 |
| Peak memory | 145628 kb |
| Host | smart-75fb46cd-1364-42af-be0e-32fbcca6855c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1580303138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1580303138 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |