| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/11.prim_esc_test.1831757764 |
| 89.45 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/18.prim_esc_test.3865794591 |
| 91.17 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/19.prim_esc_test.4067101575 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/13.prim_esc_test.27038791 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.4254688232 |
| /workspace/coverage/default/1.prim_esc_test.4114085082 |
| /workspace/coverage/default/10.prim_esc_test.360950325 |
| /workspace/coverage/default/12.prim_esc_test.1641203026 |
| /workspace/coverage/default/14.prim_esc_test.1628123976 |
| /workspace/coverage/default/15.prim_esc_test.2839293305 |
| /workspace/coverage/default/16.prim_esc_test.2678847461 |
| /workspace/coverage/default/17.prim_esc_test.2647910759 |
| /workspace/coverage/default/2.prim_esc_test.1315131643 |
| /workspace/coverage/default/3.prim_esc_test.1081627448 |
| /workspace/coverage/default/4.prim_esc_test.1743085168 |
| /workspace/coverage/default/5.prim_esc_test.1898566297 |
| /workspace/coverage/default/6.prim_esc_test.3084239730 |
| /workspace/coverage/default/7.prim_esc_test.217678356 |
| /workspace/coverage/default/8.prim_esc_test.1189213710 |
| /workspace/coverage/default/9.prim_esc_test.2136672960 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/8.prim_esc_test.1189213710 | Jul 28 04:55:00 PM PDT 24 | Jul 28 04:55:00 PM PDT 24 | 5317373 ps | ||
| T2 | /workspace/coverage/default/9.prim_esc_test.2136672960 | Jul 28 04:55:03 PM PDT 24 | Jul 28 04:55:03 PM PDT 24 | 4415940 ps | ||
| T3 | /workspace/coverage/default/5.prim_esc_test.1898566297 | Jul 28 04:55:04 PM PDT 24 | Jul 28 04:55:04 PM PDT 24 | 5210593 ps | ||
| T18 | /workspace/coverage/default/4.prim_esc_test.1743085168 | Jul 28 04:55:03 PM PDT 24 | Jul 28 04:55:03 PM PDT 24 | 5184424 ps | ||
| T4 | /workspace/coverage/default/6.prim_esc_test.3084239730 | Jul 28 04:54:56 PM PDT 24 | Jul 28 04:54:56 PM PDT 24 | 4927655 ps | ||
| T5 | /workspace/coverage/default/17.prim_esc_test.2647910759 | Jul 28 04:55:08 PM PDT 24 | Jul 28 04:55:09 PM PDT 24 | 4556428 ps | ||
| T6 | /workspace/coverage/default/11.prim_esc_test.1831757764 | Jul 28 04:55:15 PM PDT 24 | Jul 28 04:55:15 PM PDT 24 | 4810286 ps | ||
| T7 | /workspace/coverage/default/2.prim_esc_test.1315131643 | Jul 28 04:54:57 PM PDT 24 | Jul 28 04:54:58 PM PDT 24 | 4806057 ps | ||
| T14 | /workspace/coverage/default/14.prim_esc_test.1628123976 | Jul 28 04:55:03 PM PDT 24 | Jul 28 04:55:03 PM PDT 24 | 5073261 ps | ||
| T15 | /workspace/coverage/default/1.prim_esc_test.4114085082 | Jul 28 04:54:58 PM PDT 24 | Jul 28 04:54:59 PM PDT 24 | 4224550 ps | ||
| T16 | /workspace/coverage/default/13.prim_esc_test.27038791 | Jul 28 04:55:07 PM PDT 24 | Jul 28 04:55:07 PM PDT 24 | 5226097 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.360950325 | Jul 28 04:54:42 PM PDT 24 | Jul 28 04:54:43 PM PDT 24 | 4758827 ps | ||
| T8 | /workspace/coverage/default/19.prim_esc_test.4067101575 | Jul 28 04:54:55 PM PDT 24 | Jul 28 04:54:56 PM PDT 24 | 4795360 ps | ||
| T11 | /workspace/coverage/default/15.prim_esc_test.2839293305 | Jul 28 04:55:08 PM PDT 24 | Jul 28 04:55:09 PM PDT 24 | 5178448 ps | ||
| T19 | /workspace/coverage/default/16.prim_esc_test.2678847461 | Jul 28 04:54:57 PM PDT 24 | Jul 28 04:54:58 PM PDT 24 | 4787073 ps | ||
| T12 | /workspace/coverage/default/18.prim_esc_test.3865794591 | Jul 28 04:54:56 PM PDT 24 | Jul 28 04:54:57 PM PDT 24 | 5004070 ps | ||
| T9 | /workspace/coverage/default/3.prim_esc_test.1081627448 | Jul 28 04:54:55 PM PDT 24 | Jul 28 04:54:55 PM PDT 24 | 5448183 ps | ||
| T20 | /workspace/coverage/default/12.prim_esc_test.1641203026 | Jul 28 04:54:46 PM PDT 24 | Jul 28 04:54:46 PM PDT 24 | 4534407 ps | ||
| T17 | /workspace/coverage/default/7.prim_esc_test.217678356 | Jul 28 04:54:55 PM PDT 24 | Jul 28 04:54:56 PM PDT 24 | 4734799 ps | ||
| T13 | /workspace/coverage/default/0.prim_esc_test.4254688232 | Jul 28 04:54:46 PM PDT 24 | Jul 28 04:54:46 PM PDT 24 | 4626219 ps |
| Test location | /workspace/coverage/default/11.prim_esc_test.1831757764 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4810286 ps |
| CPU time | 0.36 seconds |
| Started | Jul 28 04:55:15 PM PDT 24 |
| Finished | Jul 28 04:55:15 PM PDT 24 |
| Peak memory | 146332 kb |
| Host | smart-c8564911-d1a4-41f6-950e-4bd32422208d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1831757764 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1831757764 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3865794591 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5004070 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:56 PM PDT 24 |
| Finished | Jul 28 04:54:57 PM PDT 24 |
| Peak memory | 146300 kb |
| Host | smart-af43e323-a397-4e9f-bc3f-dc7f33a701a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3865794591 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3865794591 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.4067101575 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4795360 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:55 PM PDT 24 |
| Finished | Jul 28 04:54:56 PM PDT 24 |
| Peak memory | 146384 kb |
| Host | smart-3a7f121f-8cc8-4334-832e-750c9eec197d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4067101575 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.4067101575 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.27038791 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5226097 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:55:07 PM PDT 24 |
| Finished | Jul 28 04:55:07 PM PDT 24 |
| Peak memory | 146488 kb |
| Host | smart-56a45cbd-c0bf-4d57-956c-4b2ab07a52ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=27038791 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.27038791 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.4254688232 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4626219 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:54:46 PM PDT 24 |
| Finished | Jul 28 04:54:46 PM PDT 24 |
| Peak memory | 146304 kb |
| Host | smart-da145a23-9f19-4ed8-8c4e-e854efc0dc0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254688232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.4254688232 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.4114085082 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4224550 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:58 PM PDT 24 |
| Finished | Jul 28 04:54:59 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-00c3877f-46fd-40b0-a0de-541c1cc0bed9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4114085082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.4114085082 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.360950325 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4758827 ps |
| CPU time | 0.36 seconds |
| Started | Jul 28 04:54:42 PM PDT 24 |
| Finished | Jul 28 04:54:43 PM PDT 24 |
| Peak memory | 146332 kb |
| Host | smart-01570b6d-7950-4fe4-84e4-54d2cebf7b2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=360950325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.360950325 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1641203026 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4534407 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:54:46 PM PDT 24 |
| Finished | Jul 28 04:54:46 PM PDT 24 |
| Peak memory | 146340 kb |
| Host | smart-5230995f-dabc-432c-b85e-db91f7d0c3ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1641203026 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1641203026 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1628123976 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5073261 ps |
| CPU time | 0.37 seconds |
| Started | Jul 28 04:55:03 PM PDT 24 |
| Finished | Jul 28 04:55:03 PM PDT 24 |
| Peak memory | 146348 kb |
| Host | smart-509bab94-7af6-4f9c-a580-6a75216627bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1628123976 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1628123976 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.2839293305 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5178448 ps |
| CPU time | 0.37 seconds |
| Started | Jul 28 04:55:08 PM PDT 24 |
| Finished | Jul 28 04:55:09 PM PDT 24 |
| Peak memory | 146300 kb |
| Host | smart-3260f68b-853c-4bd5-97f2-e665f9f17d09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2839293305 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2839293305 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2678847461 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4787073 ps |
| CPU time | 0.42 seconds |
| Started | Jul 28 04:54:57 PM PDT 24 |
| Finished | Jul 28 04:54:58 PM PDT 24 |
| Peak memory | 146692 kb |
| Host | smart-102eac6e-f822-4083-ba2b-ab975b87889c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2678847461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2678847461 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2647910759 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4556428 ps |
| CPU time | 0.36 seconds |
| Started | Jul 28 04:55:08 PM PDT 24 |
| Finished | Jul 28 04:55:09 PM PDT 24 |
| Peak memory | 146380 kb |
| Host | smart-e327d3c2-a00d-4397-bc7a-fcb68eceffe6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2647910759 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2647910759 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1315131643 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4806057 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:57 PM PDT 24 |
| Finished | Jul 28 04:54:58 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-10412183-015e-4654-ba85-d610cf39fef1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1315131643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1315131643 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1081627448 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5448183 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:54:55 PM PDT 24 |
| Finished | Jul 28 04:54:55 PM PDT 24 |
| Peak memory | 146348 kb |
| Host | smart-91441a97-7b18-41c9-9730-d75b2d26de0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1081627448 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1081627448 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1743085168 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5184424 ps |
| CPU time | 0.37 seconds |
| Started | Jul 28 04:55:03 PM PDT 24 |
| Finished | Jul 28 04:55:03 PM PDT 24 |
| Peak memory | 146348 kb |
| Host | smart-e68df66e-f328-4b91-930f-2d37ce747cd5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1743085168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1743085168 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1898566297 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5210593 ps |
| CPU time | 0.4 seconds |
| Started | Jul 28 04:55:04 PM PDT 24 |
| Finished | Jul 28 04:55:04 PM PDT 24 |
| Peak memory | 146372 kb |
| Host | smart-60e155f1-823d-4ff9-ae67-62cece5a76c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1898566297 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1898566297 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3084239730 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4927655 ps |
| CPU time | 0.37 seconds |
| Started | Jul 28 04:54:56 PM PDT 24 |
| Finished | Jul 28 04:54:56 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-65f0a54f-f0f7-443f-a646-f4d49a7f2ac7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3084239730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3084239730 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.217678356 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4734799 ps |
| CPU time | 0.39 seconds |
| Started | Jul 28 04:54:55 PM PDT 24 |
| Finished | Jul 28 04:54:56 PM PDT 24 |
| Peak memory | 146348 kb |
| Host | smart-febc2ae1-9cb1-4e2d-8af2-426cef955573 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=217678356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.217678356 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1189213710 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5317373 ps |
| CPU time | 0.38 seconds |
| Started | Jul 28 04:55:00 PM PDT 24 |
| Finished | Jul 28 04:55:00 PM PDT 24 |
| Peak memory | 146084 kb |
| Host | smart-6df44934-6a36-4080-8b5b-a7577eba463b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189213710 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1189213710 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2136672960 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4415940 ps |
| CPU time | 0.36 seconds |
| Started | Jul 28 04:55:03 PM PDT 24 |
| Finished | Jul 28 04:55:03 PM PDT 24 |
| Peak memory | 146348 kb |
| Host | smart-0c899b7c-f920-47e3-a70a-20f1b0e348e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2136672960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2136672960 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |