Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.29 95.41 87.80 100.00 96.43 88.89 85.19


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.74 87.74 92.66 92.66 87.80 87.80 100.00 100.00 78.57 78.57 82.22 82.22 85.19 85.19 /workspace/coverage/default/9.prim_esc_test.3377627237
90.05 2.31 93.58 0.92 87.80 0.00 100.00 0.00 89.29 10.71 84.44 2.22 85.19 0.00 /workspace/coverage/default/8.prim_esc_test.3039673416
91.17 1.12 94.50 0.92 87.80 0.00 100.00 0.00 92.86 3.57 86.67 2.22 85.19 0.00 /workspace/coverage/default/11.prim_esc_test.805095540
92.29 1.12 95.41 0.92 87.80 0.00 100.00 0.00 96.43 3.57 88.89 2.22 85.19 0.00 /workspace/coverage/default/17.prim_esc_test.1973646088

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.393651479
/workspace/coverage/default/1.prim_esc_test.2314947951
/workspace/coverage/default/10.prim_esc_test.3355322964
/workspace/coverage/default/12.prim_esc_test.3747552376
/workspace/coverage/default/13.prim_esc_test.1991293061
/workspace/coverage/default/14.prim_esc_test.3928535507
/workspace/coverage/default/15.prim_esc_test.4254832957
/workspace/coverage/default/16.prim_esc_test.676151118
/workspace/coverage/default/18.prim_esc_test.1499754678
/workspace/coverage/default/19.prim_esc_test.2632734222
/workspace/coverage/default/2.prim_esc_test.477843147
/workspace/coverage/default/3.prim_esc_test.3272008872
/workspace/coverage/default/4.prim_esc_test.813856632
/workspace/coverage/default/5.prim_esc_test.2316278012
/workspace/coverage/default/6.prim_esc_test.2880120314
/workspace/coverage/default/7.prim_esc_test.282949245



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/15.prim_esc_test.4254832957 Jul 29 04:19:18 PM PDT 24 Jul 29 04:19:18 PM PDT 24 4500624 ps
T2 /workspace/coverage/default/9.prim_esc_test.3377627237 Jul 29 04:19:29 PM PDT 24 Jul 29 04:19:30 PM PDT 24 4644678 ps
T3 /workspace/coverage/default/16.prim_esc_test.676151118 Jul 29 04:19:32 PM PDT 24 Jul 29 04:19:33 PM PDT 24 4584310 ps
T9 /workspace/coverage/default/7.prim_esc_test.282949245 Jul 29 04:19:29 PM PDT 24 Jul 29 04:19:30 PM PDT 24 4923967 ps
T10 /workspace/coverage/default/19.prim_esc_test.2632734222 Jul 29 04:19:29 PM PDT 24 Jul 29 04:19:30 PM PDT 24 4680291 ps
T15 /workspace/coverage/default/2.prim_esc_test.477843147 Jul 29 04:19:18 PM PDT 24 Jul 29 04:19:18 PM PDT 24 5097857 ps
T4 /workspace/coverage/default/5.prim_esc_test.2316278012 Jul 29 04:19:17 PM PDT 24 Jul 29 04:19:17 PM PDT 24 4777420 ps
T5 /workspace/coverage/default/18.prim_esc_test.1499754678 Jul 29 04:19:29 PM PDT 24 Jul 29 04:19:30 PM PDT 24 5144361 ps
T13 /workspace/coverage/default/14.prim_esc_test.3928535507 Jul 29 04:19:29 PM PDT 24 Jul 29 04:19:30 PM PDT 24 4816238 ps
T11 /workspace/coverage/default/13.prim_esc_test.1991293061 Jul 29 04:19:29 PM PDT 24 Jul 29 04:19:30 PM PDT 24 4776736 ps
T12 /workspace/coverage/default/17.prim_esc_test.1973646088 Jul 29 04:19:32 PM PDT 24 Jul 29 04:19:33 PM PDT 24 4924612 ps
T16 /workspace/coverage/default/3.prim_esc_test.3272008872 Jul 29 04:19:29 PM PDT 24 Jul 29 04:19:30 PM PDT 24 4246951 ps
T6 /workspace/coverage/default/0.prim_esc_test.393651479 Jul 29 04:19:28 PM PDT 24 Jul 29 04:19:29 PM PDT 24 5704495 ps
T14 /workspace/coverage/default/12.prim_esc_test.3747552376 Jul 29 04:19:29 PM PDT 24 Jul 29 04:19:30 PM PDT 24 4528651 ps
T17 /workspace/coverage/default/11.prim_esc_test.805095540 Jul 29 04:19:29 PM PDT 24 Jul 29 04:19:30 PM PDT 24 5284382 ps
T18 /workspace/coverage/default/4.prim_esc_test.813856632 Jul 29 04:19:28 PM PDT 24 Jul 29 04:19:29 PM PDT 24 5397290 ps
T7 /workspace/coverage/default/1.prim_esc_test.2314947951 Jul 29 04:19:18 PM PDT 24 Jul 29 04:19:18 PM PDT 24 5034371 ps
T19 /workspace/coverage/default/10.prim_esc_test.3355322964 Jul 29 04:19:32 PM PDT 24 Jul 29 04:19:33 PM PDT 24 5095914 ps
T8 /workspace/coverage/default/8.prim_esc_test.3039673416 Jul 29 04:19:28 PM PDT 24 Jul 29 04:19:29 PM PDT 24 4056299 ps
T20 /workspace/coverage/default/6.prim_esc_test.2880120314 Jul 29 04:19:29 PM PDT 24 Jul 29 04:19:30 PM PDT 24 5328640 ps

Test location /workspace/coverage/default/9.prim_esc_test.3377627237
Short name T2
Test name
Test status
Simulation time 4644678 ps
CPU time 0.39 seconds
Started Jul 29 04:19:29 PM PDT 24
Finished Jul 29 04:19:30 PM PDT 24
Peak memory 145316 kb
Host smart-0b5c7588-3eb9-421f-b40a-79e894449adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377627237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3377627237
Directory /workspace/9.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.3039673416
Short name T8
Test name
Test status
Simulation time 4056299 ps
CPU time 0.4 seconds
Started Jul 29 04:19:28 PM PDT 24
Finished Jul 29 04:19:29 PM PDT 24
Peak memory 144584 kb
Host smart-55143a6a-e757-4326-b7f4-cad236b8a53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039673416 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3039673416
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.805095540
Short name T17
Test name
Test status
Simulation time 5284382 ps
CPU time 0.46 seconds
Started Jul 29 04:19:29 PM PDT 24
Finished Jul 29 04:19:30 PM PDT 24
Peak memory 143864 kb
Host smart-da56c263-28fd-4ea3-9cd0-268f79b00477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805095540 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.805095540
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.1973646088
Short name T12
Test name
Test status
Simulation time 4924612 ps
CPU time 0.39 seconds
Started Jul 29 04:19:32 PM PDT 24
Finished Jul 29 04:19:33 PM PDT 24
Peak memory 146564 kb
Host smart-8f62a01c-d8af-4e53-9276-2a32a0560e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973646088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1973646088
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.393651479
Short name T6
Test name
Test status
Simulation time 5704495 ps
CPU time 0.41 seconds
Started Jul 29 04:19:28 PM PDT 24
Finished Jul 29 04:19:29 PM PDT 24
Peak memory 145624 kb
Host smart-b97d3050-a208-41e7-b9c6-fdc0c28ec22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393651479 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.393651479
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.2314947951
Short name T7
Test name
Test status
Simulation time 5034371 ps
CPU time 0.4 seconds
Started Jul 29 04:19:18 PM PDT 24
Finished Jul 29 04:19:18 PM PDT 24
Peak memory 146236 kb
Host smart-c50f6c9a-6382-4752-a58d-aff4c2ee3e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314947951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2314947951
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.3355322964
Short name T19
Test name
Test status
Simulation time 5095914 ps
CPU time 0.43 seconds
Started Jul 29 04:19:32 PM PDT 24
Finished Jul 29 04:19:33 PM PDT 24
Peak memory 146564 kb
Host smart-122e0434-ced0-4a33-8db6-71fbfb159873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355322964 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3355322964
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.3747552376
Short name T14
Test name
Test status
Simulation time 4528651 ps
CPU time 0.45 seconds
Started Jul 29 04:19:29 PM PDT 24
Finished Jul 29 04:19:30 PM PDT 24
Peak memory 143540 kb
Host smart-b5c75574-0330-4f6e-a7e2-4fdac118d85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747552376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3747552376
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.1991293061
Short name T11
Test name
Test status
Simulation time 4776736 ps
CPU time 0.41 seconds
Started Jul 29 04:19:29 PM PDT 24
Finished Jul 29 04:19:30 PM PDT 24
Peak memory 144304 kb
Host smart-a3cf3d21-ab8a-4d40-baeb-56e10e4f0e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991293061 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1991293061
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.3928535507
Short name T13
Test name
Test status
Simulation time 4816238 ps
CPU time 0.4 seconds
Started Jul 29 04:19:29 PM PDT 24
Finished Jul 29 04:19:30 PM PDT 24
Peak memory 145700 kb
Host smart-e970010d-9abb-4e57-9172-052738a54627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928535507 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3928535507
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.4254832957
Short name T1
Test name
Test status
Simulation time 4500624 ps
CPU time 0.39 seconds
Started Jul 29 04:19:18 PM PDT 24
Finished Jul 29 04:19:18 PM PDT 24
Peak memory 146376 kb
Host smart-f09910b4-5a9b-4e08-8e51-34d7291a8c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254832957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.4254832957
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.676151118
Short name T3
Test name
Test status
Simulation time 4584310 ps
CPU time 0.39 seconds
Started Jul 29 04:19:32 PM PDT 24
Finished Jul 29 04:19:33 PM PDT 24
Peak memory 146604 kb
Host smart-858ee0d0-117c-48f7-9962-a4dac909959f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676151118 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.676151118
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.1499754678
Short name T5
Test name
Test status
Simulation time 5144361 ps
CPU time 0.45 seconds
Started Jul 29 04:19:29 PM PDT 24
Finished Jul 29 04:19:30 PM PDT 24
Peak memory 144196 kb
Host smart-061a85c5-9733-4283-8cfc-405eae896775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499754678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1499754678
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.2632734222
Short name T10
Test name
Test status
Simulation time 4680291 ps
CPU time 0.45 seconds
Started Jul 29 04:19:29 PM PDT 24
Finished Jul 29 04:19:30 PM PDT 24
Peak memory 143908 kb
Host smart-f6741216-bec1-41a3-b166-84cffdec0ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632734222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2632734222
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.477843147
Short name T15
Test name
Test status
Simulation time 5097857 ps
CPU time 0.38 seconds
Started Jul 29 04:19:18 PM PDT 24
Finished Jul 29 04:19:18 PM PDT 24
Peak memory 146436 kb
Host smart-594c901d-28e4-4327-a050-d8d404347134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477843147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.477843147
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.3272008872
Short name T16
Test name
Test status
Simulation time 4246951 ps
CPU time 0.38 seconds
Started Jul 29 04:19:29 PM PDT 24
Finished Jul 29 04:19:30 PM PDT 24
Peak memory 146308 kb
Host smart-432de87d-7334-4f2d-9a88-5dd133887448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272008872 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3272008872
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.813856632
Short name T18
Test name
Test status
Simulation time 5397290 ps
CPU time 0.38 seconds
Started Jul 29 04:19:28 PM PDT 24
Finished Jul 29 04:19:29 PM PDT 24
Peak memory 146320 kb
Host smart-55219c9d-856c-42c1-8e5e-227f13ad3078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813856632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.813856632
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.2316278012
Short name T4
Test name
Test status
Simulation time 4777420 ps
CPU time 0.4 seconds
Started Jul 29 04:19:17 PM PDT 24
Finished Jul 29 04:19:17 PM PDT 24
Peak memory 146232 kb
Host smart-b47c5cea-c017-4a6b-bf68-ca97718c30e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316278012 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2316278012
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.2880120314
Short name T20
Test name
Test status
Simulation time 5328640 ps
CPU time 0.39 seconds
Started Jul 29 04:19:29 PM PDT 24
Finished Jul 29 04:19:30 PM PDT 24
Peak memory 145148 kb
Host smart-2fd61ad1-6bdd-4169-b7ff-2f12d6b992c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880120314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2880120314
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.282949245
Short name T9
Test name
Test status
Simulation time 4923967 ps
CPU time 0.45 seconds
Started Jul 29 04:19:29 PM PDT 24
Finished Jul 29 04:19:30 PM PDT 24
Peak memory 143660 kb
Host smart-be1ad8d0-166d-49bd-a8a7-6d6f45389b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282949245 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.282949245
Directory /workspace/7.prim_esc_test/latest
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