| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.17 | 94.50 | 87.80 | 100.00 | 92.86 | 86.67 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.33 | 87.33 | 92.66 | 92.66 | 85.37 | 85.37 | 100.00 | 100.00 | 78.57 | 78.57 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/4.prim_esc_test.301165316 |
| 89.45 | 2.12 | 93.58 | 0.92 | 87.80 | 2.44 | 100.00 | 0.00 | 85.71 | 7.14 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/17.prim_esc_test.122549109 |
| 91.17 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/2.prim_esc_test.3866045170 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.4254659005 |
| /workspace/coverage/default/1.prim_esc_test.435454013 |
| /workspace/coverage/default/10.prim_esc_test.1536174137 |
| /workspace/coverage/default/11.prim_esc_test.2797274587 |
| /workspace/coverage/default/12.prim_esc_test.2634368717 |
| /workspace/coverage/default/13.prim_esc_test.3938342642 |
| /workspace/coverage/default/14.prim_esc_test.3491361484 |
| /workspace/coverage/default/15.prim_esc_test.551803095 |
| /workspace/coverage/default/16.prim_esc_test.756001721 |
| /workspace/coverage/default/18.prim_esc_test.3883767077 |
| /workspace/coverage/default/19.prim_esc_test.3015523414 |
| /workspace/coverage/default/3.prim_esc_test.1457763603 |
| /workspace/coverage/default/5.prim_esc_test.3445954119 |
| /workspace/coverage/default/6.prim_esc_test.3109648235 |
| /workspace/coverage/default/7.prim_esc_test.637992653 |
| /workspace/coverage/default/8.prim_esc_test.992130082 |
| /workspace/coverage/default/9.prim_esc_test.2621026617 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/13.prim_esc_test.3938342642 | Jul 31 04:23:42 PM PDT 24 | Jul 31 04:23:43 PM PDT 24 | 4388647 ps | ||
| T2 | /workspace/coverage/default/6.prim_esc_test.3109648235 | Jul 31 04:24:08 PM PDT 24 | Jul 31 04:24:08 PM PDT 24 | 5015987 ps | ||
| T3 | /workspace/coverage/default/7.prim_esc_test.637992653 | Jul 31 04:24:52 PM PDT 24 | Jul 31 04:24:53 PM PDT 24 | 5211992 ps | ||
| T5 | /workspace/coverage/default/4.prim_esc_test.301165316 | Jul 31 04:24:20 PM PDT 24 | Jul 31 04:24:20 PM PDT 24 | 5191081 ps | ||
| T4 | /workspace/coverage/default/17.prim_esc_test.122549109 | Jul 31 04:21:07 PM PDT 24 | Jul 31 04:21:07 PM PDT 24 | 4908474 ps | ||
| T12 | /workspace/coverage/default/1.prim_esc_test.435454013 | Jul 31 04:21:54 PM PDT 24 | Jul 31 04:21:55 PM PDT 24 | 4873473 ps | ||
| T9 | /workspace/coverage/default/2.prim_esc_test.3866045170 | Jul 31 04:24:19 PM PDT 24 | Jul 31 04:24:19 PM PDT 24 | 5117771 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.1536174137 | Jul 31 04:21:23 PM PDT 24 | Jul 31 04:21:23 PM PDT 24 | 4967852 ps | ||
| T6 | /workspace/coverage/default/12.prim_esc_test.2634368717 | Jul 31 04:21:40 PM PDT 24 | Jul 31 04:21:40 PM PDT 24 | 5558246 ps | ||
| T13 | /workspace/coverage/default/5.prim_esc_test.3445954119 | Jul 31 04:22:34 PM PDT 24 | Jul 31 04:22:35 PM PDT 24 | 4636285 ps | ||
| T11 | /workspace/coverage/default/8.prim_esc_test.992130082 | Jul 31 04:24:34 PM PDT 24 | Jul 31 04:24:35 PM PDT 24 | 4995434 ps | ||
| T8 | /workspace/coverage/default/3.prim_esc_test.1457763603 | Jul 31 04:20:31 PM PDT 24 | Jul 31 04:20:31 PM PDT 24 | 5464876 ps | ||
| T14 | /workspace/coverage/default/11.prim_esc_test.2797274587 | Jul 31 04:21:07 PM PDT 24 | Jul 31 04:21:07 PM PDT 24 | 4952120 ps | ||
| T15 | /workspace/coverage/default/0.prim_esc_test.4254659005 | Jul 31 04:19:54 PM PDT 24 | Jul 31 04:19:54 PM PDT 24 | 4662599 ps | ||
| T7 | /workspace/coverage/default/15.prim_esc_test.551803095 | Jul 31 04:24:52 PM PDT 24 | Jul 31 04:24:52 PM PDT 24 | 4958005 ps | ||
| T16 | /workspace/coverage/default/16.prim_esc_test.756001721 | Jul 31 04:24:52 PM PDT 24 | Jul 31 04:24:53 PM PDT 24 | 5130609 ps | ||
| T17 | /workspace/coverage/default/14.prim_esc_test.3491361484 | Jul 31 04:20:57 PM PDT 24 | Jul 31 04:20:58 PM PDT 24 | 5094124 ps | ||
| T18 | /workspace/coverage/default/9.prim_esc_test.2621026617 | Jul 31 04:21:40 PM PDT 24 | Jul 31 04:21:40 PM PDT 24 | 5420542 ps | ||
| T19 | /workspace/coverage/default/19.prim_esc_test.3015523414 | Jul 31 04:22:58 PM PDT 24 | Jul 31 04:22:59 PM PDT 24 | 5090188 ps | ||
| T20 | /workspace/coverage/default/18.prim_esc_test.3883767077 | Jul 31 04:21:46 PM PDT 24 | Jul 31 04:21:47 PM PDT 24 | 4828033 ps |
| Test location | /workspace/coverage/default/4.prim_esc_test.301165316 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5191081 ps |
| CPU time | 0.42 seconds |
| Started | Jul 31 04:24:20 PM PDT 24 |
| Finished | Jul 31 04:24:20 PM PDT 24 |
| Peak memory | 146360 kb |
| Host | smart-7ce6a138-12e0-4005-83c5-968461b1e2d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=301165316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.301165316 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.122549109 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4908474 ps |
| CPU time | 0.42 seconds |
| Started | Jul 31 04:21:07 PM PDT 24 |
| Finished | Jul 31 04:21:07 PM PDT 24 |
| Peak memory | 146352 kb |
| Host | smart-5982f879-737e-4bc5-ade1-29c207725ec4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=122549109 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.122549109 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3866045170 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5117771 ps |
| CPU time | 0.39 seconds |
| Started | Jul 31 04:24:19 PM PDT 24 |
| Finished | Jul 31 04:24:19 PM PDT 24 |
| Peak memory | 146368 kb |
| Host | smart-0d9ff6de-3743-457f-9d2a-e36d1ede52b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3866045170 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3866045170 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.4254659005 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4662599 ps |
| CPU time | 0.39 seconds |
| Started | Jul 31 04:19:54 PM PDT 24 |
| Finished | Jul 31 04:19:54 PM PDT 24 |
| Peak memory | 147188 kb |
| Host | smart-1db05ae5-773b-459e-976d-a67c75a0feab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254659005 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.4254659005 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.435454013 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4873473 ps |
| CPU time | 0.39 seconds |
| Started | Jul 31 04:21:54 PM PDT 24 |
| Finished | Jul 31 04:21:55 PM PDT 24 |
| Peak memory | 146376 kb |
| Host | smart-3a1cda40-1956-49e0-8b46-19292a4f1299 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435454013 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.435454013 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1536174137 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4967852 ps |
| CPU time | 0.38 seconds |
| Started | Jul 31 04:21:23 PM PDT 24 |
| Finished | Jul 31 04:21:23 PM PDT 24 |
| Peak memory | 146372 kb |
| Host | smart-9d9a9c1a-e17e-4a33-9e11-2efb40f02e00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536174137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1536174137 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2797274587 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4952120 ps |
| CPU time | 0.41 seconds |
| Started | Jul 31 04:21:07 PM PDT 24 |
| Finished | Jul 31 04:21:07 PM PDT 24 |
| Peak memory | 146360 kb |
| Host | smart-c93ba9cf-5ed6-463f-8f0d-b7ad3e6b221e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2797274587 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2797274587 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2634368717 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5558246 ps |
| CPU time | 0.39 seconds |
| Started | Jul 31 04:21:40 PM PDT 24 |
| Finished | Jul 31 04:21:40 PM PDT 24 |
| Peak memory | 146324 kb |
| Host | smart-3ecad1dd-1970-4e77-bb6f-e7220e9265b0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2634368717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2634368717 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3938342642 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4388647 ps |
| CPU time | 0.39 seconds |
| Started | Jul 31 04:23:42 PM PDT 24 |
| Finished | Jul 31 04:23:43 PM PDT 24 |
| Peak memory | 146440 kb |
| Host | smart-7585ac91-5001-4571-91d5-30af493c4e57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3938342642 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3938342642 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3491361484 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5094124 ps |
| CPU time | 0.42 seconds |
| Started | Jul 31 04:20:57 PM PDT 24 |
| Finished | Jul 31 04:20:58 PM PDT 24 |
| Peak memory | 145276 kb |
| Host | smart-5b2a9a0f-d273-48f9-97e4-9e4e6fcc6dc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3491361484 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3491361484 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.551803095 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4958005 ps |
| CPU time | 0.39 seconds |
| Started | Jul 31 04:24:52 PM PDT 24 |
| Finished | Jul 31 04:24:52 PM PDT 24 |
| Peak memory | 145164 kb |
| Host | smart-5c4e565a-787f-4977-8113-3465c67556ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551803095 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.551803095 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.756001721 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5130609 ps |
| CPU time | 0.38 seconds |
| Started | Jul 31 04:24:52 PM PDT 24 |
| Finished | Jul 31 04:24:53 PM PDT 24 |
| Peak memory | 146080 kb |
| Host | smart-f9e5dfa2-de37-45e4-8666-e01e1343189c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756001721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.756001721 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3883767077 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4828033 ps |
| CPU time | 0.38 seconds |
| Started | Jul 31 04:21:46 PM PDT 24 |
| Finished | Jul 31 04:21:47 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-90f7263a-fa40-46d5-814f-9b7565ab2bfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3883767077 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3883767077 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3015523414 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5090188 ps |
| CPU time | 0.38 seconds |
| Started | Jul 31 04:22:58 PM PDT 24 |
| Finished | Jul 31 04:22:59 PM PDT 24 |
| Peak memory | 146364 kb |
| Host | smart-dd6cc2f9-0f16-4f92-9c1f-74ff5be11e19 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3015523414 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3015523414 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1457763603 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5464876 ps |
| CPU time | 0.4 seconds |
| Started | Jul 31 04:20:31 PM PDT 24 |
| Finished | Jul 31 04:20:31 PM PDT 24 |
| Peak memory | 146608 kb |
| Host | smart-cc162bab-9fae-4985-b69e-4718e2f7eac6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1457763603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1457763603 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3445954119 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4636285 ps |
| CPU time | 0.39 seconds |
| Started | Jul 31 04:22:34 PM PDT 24 |
| Finished | Jul 31 04:22:35 PM PDT 24 |
| Peak memory | 146388 kb |
| Host | smart-c7952ffb-edf3-4f63-ac43-1c528628af64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3445954119 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3445954119 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.3109648235 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5015987 ps |
| CPU time | 0.4 seconds |
| Started | Jul 31 04:24:08 PM PDT 24 |
| Finished | Jul 31 04:24:08 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-50da7328-88d8-4cc9-829a-bc8c6fcdc669 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109648235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3109648235 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.637992653 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5211992 ps |
| CPU time | 0.38 seconds |
| Started | Jul 31 04:24:52 PM PDT 24 |
| Finished | Jul 31 04:24:53 PM PDT 24 |
| Peak memory | 146080 kb |
| Host | smart-30bb5616-1655-4852-aa19-ee85c1a11950 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=637992653 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.637992653 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.992130082 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4995434 ps |
| CPU time | 0.36 seconds |
| Started | Jul 31 04:24:34 PM PDT 24 |
| Finished | Jul 31 04:24:35 PM PDT 24 |
| Peak memory | 146324 kb |
| Host | smart-be345539-e435-4d1e-b76d-a567c9e91491 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=992130082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.992130082 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2621026617 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5420542 ps |
| CPU time | 0.39 seconds |
| Started | Jul 31 04:21:40 PM PDT 24 |
| Finished | Jul 31 04:21:40 PM PDT 24 |
| Peak memory | 146288 kb |
| Host | smart-91dc7efa-e307-4d2d-8ba3-dadfa951b06f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2621026617 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2621026617 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |