| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.93 | 86.93 | 92.66 | 92.66 | 82.93 | 82.93 | 100.00 | 100.00 | 78.57 | 78.57 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/11.prim_esc_test.883817601 |
| 89.05 | 2.12 | 93.58 | 0.92 | 85.37 | 2.44 | 100.00 | 0.00 | 85.71 | 7.14 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/6.prim_esc_test.320109741 |
| 90.57 | 1.53 | 94.50 | 0.92 | 87.80 | 2.44 | 100.00 | 0.00 | 89.29 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/14.prim_esc_test.3532784253 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/4.prim_esc_test.2606285570 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspace/coverage/default/1.prim_esc_test.4010367588 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2034986417 |
| /workspace/coverage/default/10.prim_esc_test.901609148 |
| /workspace/coverage/default/12.prim_esc_test.731025114 |
| /workspace/coverage/default/13.prim_esc_test.3589889112 |
| /workspace/coverage/default/15.prim_esc_test.1278964460 |
| /workspace/coverage/default/16.prim_esc_test.657013186 |
| /workspace/coverage/default/17.prim_esc_test.2754430948 |
| /workspace/coverage/default/18.prim_esc_test.735394377 |
| /workspace/coverage/default/19.prim_esc_test.1393443647 |
| /workspace/coverage/default/2.prim_esc_test.3069241069 |
| /workspace/coverage/default/3.prim_esc_test.376505995 |
| /workspace/coverage/default/5.prim_esc_test.1483455727 |
| /workspace/coverage/default/7.prim_esc_test.197413467 |
| /workspace/coverage/default/8.prim_esc_test.1650459291 |
| /workspace/coverage/default/9.prim_esc_test.2233605030 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/11.prim_esc_test.883817601 | Aug 01 04:17:46 PM PDT 24 | Aug 01 04:17:46 PM PDT 24 | 5017735 ps | ||
| T2 | /workspace/coverage/default/15.prim_esc_test.1278964460 | Aug 01 04:17:38 PM PDT 24 | Aug 01 04:17:38 PM PDT 24 | 4493005 ps | ||
| T3 | /workspace/coverage/default/14.prim_esc_test.3532784253 | Aug 01 04:17:37 PM PDT 24 | Aug 01 04:17:37 PM PDT 24 | 4589054 ps | ||
| T6 | /workspace/coverage/default/5.prim_esc_test.1483455727 | Aug 01 04:17:46 PM PDT 24 | Aug 01 04:17:46 PM PDT 24 | 5192718 ps | ||
| T8 | /workspace/coverage/default/9.prim_esc_test.2233605030 | Aug 01 04:17:45 PM PDT 24 | Aug 01 04:17:46 PM PDT 24 | 5275876 ps | ||
| T4 | /workspace/coverage/default/12.prim_esc_test.731025114 | Aug 01 04:17:46 PM PDT 24 | Aug 01 04:17:46 PM PDT 24 | 4603331 ps | ||
| T13 | /workspace/coverage/default/3.prim_esc_test.376505995 | Aug 01 04:17:45 PM PDT 24 | Aug 01 04:17:46 PM PDT 24 | 5041463 ps | ||
| T16 | /workspace/coverage/default/19.prim_esc_test.1393443647 | Aug 01 04:17:35 PM PDT 24 | Aug 01 04:17:36 PM PDT 24 | 4942475 ps | ||
| T11 | /workspace/coverage/default/16.prim_esc_test.657013186 | Aug 01 04:17:38 PM PDT 24 | Aug 01 04:17:39 PM PDT 24 | 5144966 ps | ||
| T14 | /workspace/coverage/default/0.prim_esc_test.2034986417 | Aug 01 04:17:46 PM PDT 24 | Aug 01 04:17:47 PM PDT 24 | 4487928 ps | ||
| T15 | /workspace/coverage/default/13.prim_esc_test.3589889112 | Aug 01 04:17:45 PM PDT 24 | Aug 01 04:17:46 PM PDT 24 | 4787446 ps | ||
| T5 | /workspace/coverage/default/10.prim_esc_test.901609148 | Aug 01 04:17:37 PM PDT 24 | Aug 01 04:17:38 PM PDT 24 | 5458936 ps | ||
| T10 | /workspace/coverage/default/17.prim_esc_test.2754430948 | Aug 01 04:17:36 PM PDT 24 | Aug 01 04:17:37 PM PDT 24 | 4877186 ps | ||
| T17 | /workspace/coverage/default/8.prim_esc_test.1650459291 | Aug 01 04:17:45 PM PDT 24 | Aug 01 04:17:45 PM PDT 24 | 4824879 ps | ||
| T7 | /workspace/coverage/default/4.prim_esc_test.2606285570 | Aug 01 04:17:40 PM PDT 24 | Aug 01 04:17:40 PM PDT 24 | 4939747 ps | ||
| T12 | /workspace/coverage/default/6.prim_esc_test.320109741 | Aug 01 04:17:35 PM PDT 24 | Aug 01 04:17:35 PM PDT 24 | 4832136 ps | ||
| T18 | /workspace/coverage/default/18.prim_esc_test.735394377 | Aug 01 04:17:52 PM PDT 24 | Aug 01 04:17:53 PM PDT 24 | 5178401 ps | ||
| T19 | /workspace/coverage/default/2.prim_esc_test.3069241069 | Aug 01 04:17:52 PM PDT 24 | Aug 01 04:17:52 PM PDT 24 | 4392274 ps | ||
| T9 | /workspace/coverage/default/7.prim_esc_test.197413467 | Aug 01 04:17:45 PM PDT 24 | Aug 01 04:17:46 PM PDT 24 | 4757747 ps | ||
| T20 | /workspace/coverage/default/1.prim_esc_test.4010367588 | Aug 01 04:17:36 PM PDT 24 | Aug 01 04:17:37 PM PDT 24 | 5178939 ps |
| Test location | /workspace/coverage/default/11.prim_esc_test.883817601 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5017735 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:17:46 PM PDT 24 |
| Finished | Aug 01 04:17:46 PM PDT 24 |
| Peak memory | 146444 kb |
| Host | smart-ed446666-0728-4b3a-89c5-506f54a540c5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=883817601 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.883817601 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.320109741 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4832136 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:17:35 PM PDT 24 |
| Finished | Aug 01 04:17:35 PM PDT 24 |
| Peak memory | 146636 kb |
| Host | smart-9da2540a-f8b7-4a81-adb8-94591fd85f23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320109741 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.320109741 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3532784253 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4589054 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 04:17:37 PM PDT 24 |
| Finished | Aug 01 04:17:37 PM PDT 24 |
| Peak memory | 146148 kb |
| Host | smart-68e6821c-e75a-48d5-951a-5b1ce8a1ea92 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532784253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3532784253 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2606285570 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4939747 ps |
| CPU time | 0.37 seconds |
| Started | Aug 01 04:17:40 PM PDT 24 |
| Finished | Aug 01 04:17:40 PM PDT 24 |
| Peak memory | 146152 kb |
| Host | smart-519c460d-30bc-47ca-b39f-3058ea353929 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2606285570 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2606285570 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.4010367588 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5178939 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:17:36 PM PDT 24 |
| Finished | Aug 01 04:17:37 PM PDT 24 |
| Peak memory | 146576 kb |
| Host | smart-3c84b544-348a-4f5e-9fa7-cb433d97a9d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4010367588 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.4010367588 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2034986417 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4487928 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:17:46 PM PDT 24 |
| Finished | Aug 01 04:17:47 PM PDT 24 |
| Peak memory | 146392 kb |
| Host | smart-ab2bcfc7-ae41-4064-83cd-cbca2abe3d97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2034986417 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2034986417 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.901609148 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5458936 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 04:17:37 PM PDT 24 |
| Finished | Aug 01 04:17:38 PM PDT 24 |
| Peak memory | 146636 kb |
| Host | smart-ff36fe77-f57e-4728-9326-8f9c91164ddf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=901609148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.901609148 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.731025114 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4603331 ps |
| CPU time | 0.37 seconds |
| Started | Aug 01 04:17:46 PM PDT 24 |
| Finished | Aug 01 04:17:46 PM PDT 24 |
| Peak memory | 146456 kb |
| Host | smart-7f839bf5-66af-46cf-a94c-67cb90b06708 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=731025114 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.731025114 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3589889112 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4787446 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:17:45 PM PDT 24 |
| Finished | Aug 01 04:17:46 PM PDT 24 |
| Peak memory | 146440 kb |
| Host | smart-58c3d027-0543-4331-84eb-15e49f09cffa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3589889112 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3589889112 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1278964460 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4493005 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:17:38 PM PDT 24 |
| Finished | Aug 01 04:17:38 PM PDT 24 |
| Peak memory | 145496 kb |
| Host | smart-cc8bb084-3c7d-4317-b85f-049653e3fea4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1278964460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1278964460 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.657013186 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5144966 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:17:38 PM PDT 24 |
| Finished | Aug 01 04:17:39 PM PDT 24 |
| Peak memory | 146452 kb |
| Host | smart-1a2fd2c8-e3d0-43c8-bc85-89432112f00e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=657013186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.657013186 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2754430948 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4877186 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:17:36 PM PDT 24 |
| Finished | Aug 01 04:17:37 PM PDT 24 |
| Peak memory | 146640 kb |
| Host | smart-0383c140-8bb8-4a83-b850-f13dce008cb7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2754430948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2754430948 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.735394377 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5178401 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 04:17:52 PM PDT 24 |
| Finished | Aug 01 04:17:53 PM PDT 24 |
| Peak memory | 146456 kb |
| Host | smart-fb5506b6-002c-4862-a0b7-8677c6786a20 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=735394377 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.735394377 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1393443647 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4942475 ps |
| CPU time | 0.41 seconds |
| Started | Aug 01 04:17:35 PM PDT 24 |
| Finished | Aug 01 04:17:36 PM PDT 24 |
| Peak memory | 146640 kb |
| Host | smart-575b325d-c0c7-4b5b-a6a4-87b0f6e632da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1393443647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1393443647 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3069241069 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4392274 ps |
| CPU time | 0.39 seconds |
| Started | Aug 01 04:17:52 PM PDT 24 |
| Finished | Aug 01 04:17:52 PM PDT 24 |
| Peak memory | 146456 kb |
| Host | smart-8d5dc93e-d84e-44ad-9ac3-cf2d3d93f228 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069241069 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3069241069 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.376505995 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5041463 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 04:17:45 PM PDT 24 |
| Finished | Aug 01 04:17:46 PM PDT 24 |
| Peak memory | 146396 kb |
| Host | smart-9e2922b4-db82-4987-a434-692cc0ae6aa6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=376505995 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.376505995 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1483455727 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5192718 ps |
| CPU time | 0.38 seconds |
| Started | Aug 01 04:17:46 PM PDT 24 |
| Finished | Aug 01 04:17:46 PM PDT 24 |
| Peak memory | 146392 kb |
| Host | smart-d0c68ece-2a2e-4ea0-9b32-6529dde71b9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483455727 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1483455727 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.197413467 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4757747 ps |
| CPU time | 0.49 seconds |
| Started | Aug 01 04:17:45 PM PDT 24 |
| Finished | Aug 01 04:17:46 PM PDT 24 |
| Peak memory | 146064 kb |
| Host | smart-29f93b27-518e-42bb-9e25-39ddd5fa9313 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=197413467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.197413467 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1650459291 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4824879 ps |
| CPU time | 0.37 seconds |
| Started | Aug 01 04:17:45 PM PDT 24 |
| Finished | Aug 01 04:17:45 PM PDT 24 |
| Peak memory | 146456 kb |
| Host | smart-aafcfcbe-253b-4279-b731-c0512377f63a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1650459291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1650459291 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2233605030 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5275876 ps |
| CPU time | 0.37 seconds |
| Started | Aug 01 04:17:45 PM PDT 24 |
| Finished | Aug 01 04:17:46 PM PDT 24 |
| Peak memory | 146444 kb |
| Host | smart-da657b2c-5dae-4aec-9dfb-9c89e1bc3329 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2233605030 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2233605030 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |