Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.29 95.41 87.80 100.00 96.43 88.89 85.19


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.74 86.74 92.66 92.66 85.37 85.37 100.00 100.00 75.00 75.00 82.22 82.22 85.19 85.19 /workspace/coverage/default/12.prim_esc_test.4026312919
89.45 2.72 93.58 0.92 87.80 2.44 100.00 0.00 85.71 10.71 84.44 2.22 85.19 0.00 /workspace/coverage/default/17.prim_esc_test.1368932869
91.17 1.71 94.50 0.92 87.80 0.00 100.00 0.00 92.86 7.14 86.67 2.22 85.19 0.00 /workspace/coverage/default/10.prim_esc_test.2408302390
92.29 1.12 95.41 0.92 87.80 0.00 100.00 0.00 96.43 3.57 88.89 2.22 85.19 0.00 /workspace/coverage/default/0.prim_esc_test.3768916833

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.811467547
/workspace/coverage/default/11.prim_esc_test.1829398667
/workspace/coverage/default/13.prim_esc_test.2483213917
/workspace/coverage/default/14.prim_esc_test.1420930658
/workspace/coverage/default/15.prim_esc_test.1314199316
/workspace/coverage/default/16.prim_esc_test.3365541270
/workspace/coverage/default/18.prim_esc_test.1977096346
/workspace/coverage/default/19.prim_esc_test.89698857
/workspace/coverage/default/2.prim_esc_test.821319182
/workspace/coverage/default/3.prim_esc_test.3944218829
/workspace/coverage/default/4.prim_esc_test.1246718912
/workspace/coverage/default/5.prim_esc_test.1624741899
/workspace/coverage/default/6.prim_esc_test.2976115146
/workspace/coverage/default/7.prim_esc_test.2564453614
/workspace/coverage/default/8.prim_esc_test.976413798
/workspace/coverage/default/9.prim_esc_test.1877913541



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/13.prim_esc_test.2483213917 Aug 02 04:23:12 PM PDT 24 Aug 02 04:23:13 PM PDT 24 5020527 ps
T2 /workspace/coverage/default/9.prim_esc_test.1877913541 Aug 02 04:23:11 PM PDT 24 Aug 02 04:23:12 PM PDT 24 4979013 ps
T3 /workspace/coverage/default/15.prim_esc_test.1314199316 Aug 02 04:23:14 PM PDT 24 Aug 02 04:23:14 PM PDT 24 5233190 ps
T4 /workspace/coverage/default/17.prim_esc_test.1368932869 Aug 02 04:23:02 PM PDT 24 Aug 02 04:23:03 PM PDT 24 4877263 ps
T12 /workspace/coverage/default/10.prim_esc_test.2408302390 Aug 02 04:23:12 PM PDT 24 Aug 02 04:23:13 PM PDT 24 4381042 ps
T5 /workspace/coverage/default/3.prim_esc_test.3944218829 Aug 02 04:23:17 PM PDT 24 Aug 02 04:23:18 PM PDT 24 5145988 ps
T6 /workspace/coverage/default/12.prim_esc_test.4026312919 Aug 02 04:23:13 PM PDT 24 Aug 02 04:23:14 PM PDT 24 5121240 ps
T14 /workspace/coverage/default/7.prim_esc_test.2564453614 Aug 02 04:23:02 PM PDT 24 Aug 02 04:23:02 PM PDT 24 5157823 ps
T8 /workspace/coverage/default/19.prim_esc_test.89698857 Aug 02 04:23:12 PM PDT 24 Aug 02 04:23:12 PM PDT 24 4447832 ps
T16 /workspace/coverage/default/2.prim_esc_test.821319182 Aug 02 04:23:14 PM PDT 24 Aug 02 04:23:15 PM PDT 24 4659363 ps
T15 /workspace/coverage/default/1.prim_esc_test.811467547 Aug 02 04:23:18 PM PDT 24 Aug 02 04:23:19 PM PDT 24 5313799 ps
T7 /workspace/coverage/default/11.prim_esc_test.1829398667 Aug 02 04:23:12 PM PDT 24 Aug 02 04:23:12 PM PDT 24 4951692 ps
T9 /workspace/coverage/default/0.prim_esc_test.3768916833 Aug 02 04:23:02 PM PDT 24 Aug 02 04:23:03 PM PDT 24 4898184 ps
T18 /workspace/coverage/default/14.prim_esc_test.1420930658 Aug 02 04:23:12 PM PDT 24 Aug 02 04:23:13 PM PDT 24 4879832 ps
T13 /workspace/coverage/default/5.prim_esc_test.1624741899 Aug 02 04:23:11 PM PDT 24 Aug 02 04:23:12 PM PDT 24 4914390 ps
T17 /workspace/coverage/default/6.prim_esc_test.2976115146 Aug 02 04:23:14 PM PDT 24 Aug 02 04:23:15 PM PDT 24 5011477 ps
T19 /workspace/coverage/default/8.prim_esc_test.976413798 Aug 02 04:23:18 PM PDT 24 Aug 02 04:23:19 PM PDT 24 4919476 ps
T10 /workspace/coverage/default/18.prim_esc_test.1977096346 Aug 02 04:23:11 PM PDT 24 Aug 02 04:23:12 PM PDT 24 5349316 ps
T11 /workspace/coverage/default/4.prim_esc_test.1246718912 Aug 02 04:23:12 PM PDT 24 Aug 02 04:23:13 PM PDT 24 5224482 ps
T20 /workspace/coverage/default/16.prim_esc_test.3365541270 Aug 02 04:23:11 PM PDT 24 Aug 02 04:23:12 PM PDT 24 4694113 ps

Test location /workspace/coverage/default/12.prim_esc_test.4026312919
Short name T6
Test name
Test status
Simulation time 5121240 ps
CPU time 0.37 seconds
Started Aug 02 04:23:13 PM PDT 24
Finished Aug 02 04:23:14 PM PDT 24
Peak memory 146384 kb
Host smart-350e1de5-69c4-4254-8ca0-288a99d06ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026312919 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.4026312919
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.1368932869
Short name T4
Test name
Test status
Simulation time 4877263 ps
CPU time 0.4 seconds
Started Aug 02 04:23:02 PM PDT 24
Finished Aug 02 04:23:03 PM PDT 24
Peak memory 145748 kb
Host smart-757db92a-b0e1-49fa-bf63-d49f83b43fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368932869 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1368932869
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.2408302390
Short name T12
Test name
Test status
Simulation time 4381042 ps
CPU time 0.37 seconds
Started Aug 02 04:23:12 PM PDT 24
Finished Aug 02 04:23:13 PM PDT 24
Peak memory 146420 kb
Host smart-995376a2-493e-4f55-b833-816a35096807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408302390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2408302390
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.3768916833
Short name T9
Test name
Test status
Simulation time 4898184 ps
CPU time 0.41 seconds
Started Aug 02 04:23:02 PM PDT 24
Finished Aug 02 04:23:03 PM PDT 24
Peak memory 145740 kb
Host smart-9789a2fc-8dd2-47a7-a966-948a2c23d3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768916833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3768916833
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.811467547
Short name T15
Test name
Test status
Simulation time 5313799 ps
CPU time 0.37 seconds
Started Aug 02 04:23:18 PM PDT 24
Finished Aug 02 04:23:19 PM PDT 24
Peak memory 146132 kb
Host smart-30a22168-72ce-4234-b614-b2ce662cb146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811467547 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.811467547
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.1829398667
Short name T7
Test name
Test status
Simulation time 4951692 ps
CPU time 0.38 seconds
Started Aug 02 04:23:12 PM PDT 24
Finished Aug 02 04:23:12 PM PDT 24
Peak memory 146388 kb
Host smart-bf41e596-0644-449b-961c-b42ea9eaa9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829398667 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1829398667
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.2483213917
Short name T1
Test name
Test status
Simulation time 5020527 ps
CPU time 0.37 seconds
Started Aug 02 04:23:12 PM PDT 24
Finished Aug 02 04:23:13 PM PDT 24
Peak memory 146420 kb
Host smart-4e9614d3-ddd5-458e-b995-d34b4261a5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483213917 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2483213917
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.1420930658
Short name T18
Test name
Test status
Simulation time 4879832 ps
CPU time 0.37 seconds
Started Aug 02 04:23:12 PM PDT 24
Finished Aug 02 04:23:13 PM PDT 24
Peak memory 146388 kb
Host smart-2bac9ece-458d-463f-a794-3244c750eb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420930658 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1420930658
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.1314199316
Short name T3
Test name
Test status
Simulation time 5233190 ps
CPU time 0.4 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:23:14 PM PDT 24
Peak memory 146384 kb
Host smart-f13a5268-75b4-4fa2-a7e9-3f690e6510e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314199316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1314199316
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.3365541270
Short name T20
Test name
Test status
Simulation time 4694113 ps
CPU time 0.37 seconds
Started Aug 02 04:23:11 PM PDT 24
Finished Aug 02 04:23:12 PM PDT 24
Peak memory 146424 kb
Host smart-5b67a8f4-c645-4629-9ef0-937eb110b654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365541270 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3365541270
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.1977096346
Short name T10
Test name
Test status
Simulation time 5349316 ps
CPU time 0.38 seconds
Started Aug 02 04:23:11 PM PDT 24
Finished Aug 02 04:23:12 PM PDT 24
Peak memory 146420 kb
Host smart-d7cd8592-9199-45ed-bf18-2823cb63034d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977096346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1977096346
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.89698857
Short name T8
Test name
Test status
Simulation time 4447832 ps
CPU time 0.39 seconds
Started Aug 02 04:23:12 PM PDT 24
Finished Aug 02 04:23:12 PM PDT 24
Peak memory 146404 kb
Host smart-35ab454e-a595-47c2-b22b-24904801df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89698857 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.89698857
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.821319182
Short name T16
Test name
Test status
Simulation time 4659363 ps
CPU time 0.38 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:23:15 PM PDT 24
Peak memory 146424 kb
Host smart-3fdb8cbe-d361-4bbb-b62e-33e40e892eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821319182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.821319182
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.3944218829
Short name T5
Test name
Test status
Simulation time 5145988 ps
CPU time 0.38 seconds
Started Aug 02 04:23:17 PM PDT 24
Finished Aug 02 04:23:18 PM PDT 24
Peak memory 146424 kb
Host smart-76339005-a8a8-40dc-83d0-d4c8f5981604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944218829 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3944218829
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.1246718912
Short name T11
Test name
Test status
Simulation time 5224482 ps
CPU time 0.38 seconds
Started Aug 02 04:23:12 PM PDT 24
Finished Aug 02 04:23:13 PM PDT 24
Peak memory 146388 kb
Host smart-82e2b406-ddeb-4578-9ac5-fd5e83747bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246718912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1246718912
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.1624741899
Short name T13
Test name
Test status
Simulation time 4914390 ps
CPU time 0.37 seconds
Started Aug 02 04:23:11 PM PDT 24
Finished Aug 02 04:23:12 PM PDT 24
Peak memory 146424 kb
Host smart-b7147ff2-de55-41a1-8322-237ff01db440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624741899 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1624741899
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.2976115146
Short name T17
Test name
Test status
Simulation time 5011477 ps
CPU time 0.37 seconds
Started Aug 02 04:23:14 PM PDT 24
Finished Aug 02 04:23:15 PM PDT 24
Peak memory 146388 kb
Host smart-a0d68242-68b6-4cf5-8251-2fa26259da18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976115146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2976115146
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.2564453614
Short name T14
Test name
Test status
Simulation time 5157823 ps
CPU time 0.41 seconds
Started Aug 02 04:23:02 PM PDT 24
Finished Aug 02 04:23:02 PM PDT 24
Peak memory 145740 kb
Host smart-467fe9c5-1ffd-4e31-a25a-8f6e2f5a98bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564453614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2564453614
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.976413798
Short name T19
Test name
Test status
Simulation time 4919476 ps
CPU time 0.37 seconds
Started Aug 02 04:23:18 PM PDT 24
Finished Aug 02 04:23:19 PM PDT 24
Peak memory 146172 kb
Host smart-7506b2ff-f03a-47f5-828a-d203936e23d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976413798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.976413798
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.1877913541
Short name T2
Test name
Test status
Simulation time 4979013 ps
CPU time 0.36 seconds
Started Aug 02 04:23:11 PM PDT 24
Finished Aug 02 04:23:12 PM PDT 24
Peak memory 146416 kb
Host smart-78eae4d3-9c1a-4eeb-9e4e-7fb85dc3edd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877913541 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1877913541
Directory /workspace/9.prim_esc_test/latest
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