| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.47 | 85.47 | 90.83 | 90.83 | 85.37 | 85.37 | 100.00 | 100.00 | 71.43 | 71.43 | 80.00 | 80.00 | 85.19 | 85.19 | /workspace/coverage/default/11.prim_esc_test.304079955 |
| 87.86 | 2.39 | 93.58 | 2.75 | 85.37 | 0.00 | 100.00 | 0.00 | 78.57 | 7.14 | 84.44 | 4.44 | 85.19 | 0.00 | /workspace/coverage/default/1.prim_esc_test.2443916280 |
| 89.98 | 2.12 | 94.50 | 0.92 | 87.80 | 2.44 | 100.00 | 0.00 | 85.71 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/13.prim_esc_test.622012709 |
| 91.17 | 1.19 | 94.50 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 0.00 | 85.19 | 0.00 | /workspace/coverage/default/6.prim_esc_test.1203984422 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/15.prim_esc_test.3626635183 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2707305289 |
| /workspace/coverage/default/10.prim_esc_test.205498226 |
| /workspace/coverage/default/12.prim_esc_test.3513344549 |
| /workspace/coverage/default/14.prim_esc_test.1748284220 |
| /workspace/coverage/default/16.prim_esc_test.2423651275 |
| /workspace/coverage/default/17.prim_esc_test.3922556058 |
| /workspace/coverage/default/18.prim_esc_test.2997054421 |
| /workspace/coverage/default/19.prim_esc_test.2492684971 |
| /workspace/coverage/default/2.prim_esc_test.1257427471 |
| /workspace/coverage/default/3.prim_esc_test.4173580814 |
| /workspace/coverage/default/4.prim_esc_test.2307181127 |
| /workspace/coverage/default/5.prim_esc_test.294879546 |
| /workspace/coverage/default/7.prim_esc_test.3466925240 |
| /workspace/coverage/default/8.prim_esc_test.3633198015 |
| /workspace/coverage/default/9.prim_esc_test.3554436312 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_esc_test.3513344549 | Aug 03 04:16:10 PM PDT 24 | Aug 03 04:16:11 PM PDT 24 | 5089549 ps | ||
| T2 | /workspace/coverage/default/6.prim_esc_test.1203984422 | Aug 03 04:17:07 PM PDT 24 | Aug 03 04:17:07 PM PDT 24 | 4527715 ps | ||
| T3 | /workspace/coverage/default/0.prim_esc_test.2707305289 | Aug 03 04:16:10 PM PDT 24 | Aug 03 04:16:11 PM PDT 24 | 5316845 ps | ||
| T9 | /workspace/coverage/default/9.prim_esc_test.3554436312 | Aug 03 04:16:29 PM PDT 24 | Aug 03 04:16:30 PM PDT 24 | 4659545 ps | ||
| T4 | /workspace/coverage/default/7.prim_esc_test.3466925240 | Aug 03 04:16:10 PM PDT 24 | Aug 03 04:16:11 PM PDT 24 | 5526846 ps | ||
| T17 | /workspace/coverage/default/3.prim_esc_test.4173580814 | Aug 03 04:16:06 PM PDT 24 | Aug 03 04:16:07 PM PDT 24 | 4300925 ps | ||
| T6 | /workspace/coverage/default/5.prim_esc_test.294879546 | Aug 03 04:16:10 PM PDT 24 | Aug 03 04:16:11 PM PDT 24 | 5449912 ps | ||
| T7 | /workspace/coverage/default/11.prim_esc_test.304079955 | Aug 03 04:16:41 PM PDT 24 | Aug 03 04:16:41 PM PDT 24 | 4827480 ps | ||
| T13 | /workspace/coverage/default/16.prim_esc_test.2423651275 | Aug 03 04:16:28 PM PDT 24 | Aug 03 04:16:28 PM PDT 24 | 5152249 ps | ||
| T18 | /workspace/coverage/default/4.prim_esc_test.2307181127 | Aug 03 04:16:03 PM PDT 24 | Aug 03 04:16:03 PM PDT 24 | 4226690 ps | ||
| T5 | /workspace/coverage/default/14.prim_esc_test.1748284220 | Aug 03 04:16:03 PM PDT 24 | Aug 03 04:16:04 PM PDT 24 | 5132298 ps | ||
| T11 | /workspace/coverage/default/2.prim_esc_test.1257427471 | Aug 03 04:16:10 PM PDT 24 | Aug 03 04:16:11 PM PDT 24 | 4562290 ps | ||
| T14 | /workspace/coverage/default/17.prim_esc_test.3922556058 | Aug 03 04:16:41 PM PDT 24 | Aug 03 04:16:41 PM PDT 24 | 5101853 ps | ||
| T12 | /workspace/coverage/default/13.prim_esc_test.622012709 | Aug 03 04:16:06 PM PDT 24 | Aug 03 04:16:07 PM PDT 24 | 5750780 ps | ||
| T8 | /workspace/coverage/default/1.prim_esc_test.2443916280 | Aug 03 04:16:10 PM PDT 24 | Aug 03 04:16:11 PM PDT 24 | 4173069 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.205498226 | Aug 03 04:16:06 PM PDT 24 | Aug 03 04:16:07 PM PDT 24 | 4467999 ps | ||
| T15 | /workspace/coverage/default/15.prim_esc_test.3626635183 | Aug 03 04:16:06 PM PDT 24 | Aug 03 04:16:07 PM PDT 24 | 5012325 ps | ||
| T16 | /workspace/coverage/default/8.prim_esc_test.3633198015 | Aug 03 04:16:05 PM PDT 24 | Aug 03 04:16:06 PM PDT 24 | 4960457 ps | ||
| T20 | /workspace/coverage/default/19.prim_esc_test.2492684971 | Aug 03 04:16:07 PM PDT 24 | Aug 03 04:16:08 PM PDT 24 | 5146047 ps | ||
| T19 | /workspace/coverage/default/18.prim_esc_test.2997054421 | Aug 03 04:16:10 PM PDT 24 | Aug 03 04:16:11 PM PDT 24 | 5434586 ps |
| Test location | /workspace/coverage/default/11.prim_esc_test.304079955 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4827480 ps |
| CPU time | 0.41 seconds |
| Started | Aug 03 04:16:41 PM PDT 24 |
| Finished | Aug 03 04:16:41 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-608279f5-c7b9-48a2-88af-ae7546f2d2d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=304079955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.304079955 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2443916280 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4173069 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:16:10 PM PDT 24 |
| Finished | Aug 03 04:16:11 PM PDT 24 |
| Peak memory | 146060 kb |
| Host | smart-969c6a02-d2a6-44f9-bcbc-c30a57296500 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2443916280 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2443916280 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.622012709 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5750780 ps |
| CPU time | 0.52 seconds |
| Started | Aug 03 04:16:06 PM PDT 24 |
| Finished | Aug 03 04:16:07 PM PDT 24 |
| Peak memory | 145452 kb |
| Host | smart-62c65a8b-b3a0-4c62-b159-2034405ddb67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622012709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.622012709 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.1203984422 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4527715 ps |
| CPU time | 0.38 seconds |
| Started | Aug 03 04:17:07 PM PDT 24 |
| Finished | Aug 03 04:17:07 PM PDT 24 |
| Peak memory | 146300 kb |
| Host | smart-a836f9b7-801f-46bb-a739-923d0369d0e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1203984422 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1203984422 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3626635183 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5012325 ps |
| CPU time | 0.43 seconds |
| Started | Aug 03 04:16:06 PM PDT 24 |
| Finished | Aug 03 04:16:07 PM PDT 24 |
| Peak memory | 145372 kb |
| Host | smart-9879884a-00b2-4c7b-976a-dc11f1f33517 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3626635183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3626635183 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2707305289 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5316845 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:16:10 PM PDT 24 |
| Finished | Aug 03 04:16:11 PM PDT 24 |
| Peak memory | 146136 kb |
| Host | smart-78fa3cbb-677f-4e7a-aef1-867675d6e408 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2707305289 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2707305289 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.205498226 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4467999 ps |
| CPU time | 0.49 seconds |
| Started | Aug 03 04:16:06 PM PDT 24 |
| Finished | Aug 03 04:16:07 PM PDT 24 |
| Peak memory | 145604 kb |
| Host | smart-3c9b5c3d-1d3a-4fd4-b2c1-f7941f57c0f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205498226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.205498226 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3513344549 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5089549 ps |
| CPU time | 0.43 seconds |
| Started | Aug 03 04:16:10 PM PDT 24 |
| Finished | Aug 03 04:16:11 PM PDT 24 |
| Peak memory | 145436 kb |
| Host | smart-1da570be-429b-4d2e-b484-e668493ff6eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513344549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3513344549 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1748284220 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5132298 ps |
| CPU time | 0.42 seconds |
| Started | Aug 03 04:16:03 PM PDT 24 |
| Finished | Aug 03 04:16:04 PM PDT 24 |
| Peak memory | 146636 kb |
| Host | smart-7169e5f9-44ae-49dd-a9df-295fb4d6f01e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1748284220 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1748284220 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2423651275 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5152249 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:16:28 PM PDT 24 |
| Finished | Aug 03 04:16:28 PM PDT 24 |
| Peak memory | 146284 kb |
| Host | smart-5ccf965c-11ad-4e3c-a752-d5e5be58db32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423651275 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2423651275 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3922556058 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5101853 ps |
| CPU time | 0.42 seconds |
| Started | Aug 03 04:16:41 PM PDT 24 |
| Finished | Aug 03 04:16:41 PM PDT 24 |
| Peak memory | 146304 kb |
| Host | smart-3de9c5bd-7d0b-44f6-9afe-b4af63506dff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3922556058 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3922556058 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2997054421 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5434586 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:16:10 PM PDT 24 |
| Finished | Aug 03 04:16:11 PM PDT 24 |
| Peak memory | 145528 kb |
| Host | smart-8bad0ef6-5f68-4ba1-aa11-b8a69bf1c9db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2997054421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2997054421 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2492684971 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5146047 ps |
| CPU time | 0.43 seconds |
| Started | Aug 03 04:16:07 PM PDT 24 |
| Finished | Aug 03 04:16:08 PM PDT 24 |
| Peak memory | 146656 kb |
| Host | smart-09580c94-846b-42fd-879e-58f488815e04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492684971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2492684971 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1257427471 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4562290 ps |
| CPU time | 0.45 seconds |
| Started | Aug 03 04:16:10 PM PDT 24 |
| Finished | Aug 03 04:16:11 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-0054b9f6-aca2-4d7d-a58f-c694711e46d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1257427471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1257427471 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.4173580814 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4300925 ps |
| CPU time | 0.51 seconds |
| Started | Aug 03 04:16:06 PM PDT 24 |
| Finished | Aug 03 04:16:07 PM PDT 24 |
| Peak memory | 145280 kb |
| Host | smart-abd447e0-16d0-42be-bec7-29f0de734788 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4173580814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.4173580814 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2307181127 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4226690 ps |
| CPU time | 0.39 seconds |
| Started | Aug 03 04:16:03 PM PDT 24 |
| Finished | Aug 03 04:16:03 PM PDT 24 |
| Peak memory | 146628 kb |
| Host | smart-b4a5f195-3800-4828-b20b-36bf67d24097 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2307181127 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2307181127 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.294879546 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5449912 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:16:10 PM PDT 24 |
| Finished | Aug 03 04:16:11 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-99e6f6bf-3554-43d9-8473-75349ad6dca4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=294879546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.294879546 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3466925240 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5526846 ps |
| CPU time | 0.4 seconds |
| Started | Aug 03 04:16:10 PM PDT 24 |
| Finished | Aug 03 04:16:11 PM PDT 24 |
| Peak memory | 145584 kb |
| Host | smart-625f88f8-15b2-4c43-979e-30d4783c9a58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3466925240 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3466925240 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3633198015 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4960457 ps |
| CPU time | 0.46 seconds |
| Started | Aug 03 04:16:05 PM PDT 24 |
| Finished | Aug 03 04:16:06 PM PDT 24 |
| Peak memory | 146684 kb |
| Host | smart-e134472c-9ea3-47a8-9a7b-bc9d22861639 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3633198015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3633198015 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3554436312 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4659545 ps |
| CPU time | 0.37 seconds |
| Started | Aug 03 04:16:29 PM PDT 24 |
| Finished | Aug 03 04:16:30 PM PDT 24 |
| Peak memory | 146300 kb |
| Host | smart-2e6a14eb-f47a-47bf-b7be-4e6c4706fc2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3554436312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3554436312 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |