| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/9.prim_esc_test.1143982989 |
| 89.45 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/10.prim_esc_test.1040990253 |
| 91.17 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/14.prim_esc_test.2183905978 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/18.prim_esc_test.2424809129 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.3180421569 |
| /workspace/coverage/default/1.prim_esc_test.3082973121 |
| /workspace/coverage/default/11.prim_esc_test.3191547383 |
| /workspace/coverage/default/12.prim_esc_test.3428942143 |
| /workspace/coverage/default/13.prim_esc_test.4045329312 |
| /workspace/coverage/default/15.prim_esc_test.207073830 |
| /workspace/coverage/default/16.prim_esc_test.2475841824 |
| /workspace/coverage/default/17.prim_esc_test.3844619620 |
| /workspace/coverage/default/19.prim_esc_test.1194721868 |
| /workspace/coverage/default/2.prim_esc_test.3111861043 |
| /workspace/coverage/default/3.prim_esc_test.2615035495 |
| /workspace/coverage/default/4.prim_esc_test.179561225 |
| /workspace/coverage/default/5.prim_esc_test.1100704616 |
| /workspace/coverage/default/6.prim_esc_test.2494093444 |
| /workspace/coverage/default/7.prim_esc_test.3257977696 |
| /workspace/coverage/default/8.prim_esc_test.3540157136 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_esc_test.1143982989 | Aug 05 04:21:46 PM PDT 24 | Aug 05 04:21:47 PM PDT 24 | 5307024 ps | ||
| T2 | /workspace/coverage/default/6.prim_esc_test.2494093444 | Aug 05 04:21:56 PM PDT 24 | Aug 05 04:21:56 PM PDT 24 | 4133410 ps | ||
| T3 | /workspace/coverage/default/3.prim_esc_test.2615035495 | Aug 05 04:22:24 PM PDT 24 | Aug 05 04:22:25 PM PDT 24 | 4336197 ps | ||
| T4 | /workspace/coverage/default/14.prim_esc_test.2183905978 | Aug 05 04:19:28 PM PDT 24 | Aug 05 04:19:29 PM PDT 24 | 4327215 ps | ||
| T11 | /workspace/coverage/default/13.prim_esc_test.4045329312 | Aug 05 04:20:26 PM PDT 24 | Aug 05 04:20:26 PM PDT 24 | 4894606 ps | ||
| T6 | /workspace/coverage/default/17.prim_esc_test.3844619620 | Aug 05 04:22:11 PM PDT 24 | Aug 05 04:22:11 PM PDT 24 | 4809626 ps | ||
| T7 | /workspace/coverage/default/8.prim_esc_test.3540157136 | Aug 05 04:22:24 PM PDT 24 | Aug 05 04:22:25 PM PDT 24 | 5474024 ps | ||
| T8 | /workspace/coverage/default/16.prim_esc_test.2475841824 | Aug 05 04:22:53 PM PDT 24 | Aug 05 04:22:54 PM PDT 24 | 5071174 ps | ||
| T5 | /workspace/coverage/default/18.prim_esc_test.2424809129 | Aug 05 04:21:49 PM PDT 24 | Aug 05 04:21:50 PM PDT 24 | 4818828 ps | ||
| T9 | /workspace/coverage/default/10.prim_esc_test.1040990253 | Aug 05 04:22:54 PM PDT 24 | Aug 05 04:22:54 PM PDT 24 | 4607075 ps | ||
| T12 | /workspace/coverage/default/0.prim_esc_test.3180421569 | Aug 05 04:21:55 PM PDT 24 | Aug 05 04:21:56 PM PDT 24 | 5053098 ps | ||
| T13 | /workspace/coverage/default/5.prim_esc_test.1100704616 | Aug 05 04:21:53 PM PDT 24 | Aug 05 04:21:54 PM PDT 24 | 5416951 ps | ||
| T14 | /workspace/coverage/default/4.prim_esc_test.179561225 | Aug 05 04:21:53 PM PDT 24 | Aug 05 04:21:54 PM PDT 24 | 4831707 ps | ||
| T10 | /workspace/coverage/default/12.prim_esc_test.3428942143 | Aug 05 04:21:56 PM PDT 24 | Aug 05 04:21:56 PM PDT 24 | 5328194 ps | ||
| T15 | /workspace/coverage/default/1.prim_esc_test.3082973121 | Aug 05 04:21:53 PM PDT 24 | Aug 05 04:21:54 PM PDT 24 | 4852578 ps | ||
| T16 | /workspace/coverage/default/2.prim_esc_test.3111861043 | Aug 05 04:21:56 PM PDT 24 | Aug 05 04:21:56 PM PDT 24 | 5296560 ps | ||
| T17 | /workspace/coverage/default/15.prim_esc_test.207073830 | Aug 05 04:22:11 PM PDT 24 | Aug 05 04:22:12 PM PDT 24 | 4805567 ps | ||
| T18 | /workspace/coverage/default/7.prim_esc_test.3257977696 | Aug 05 04:22:08 PM PDT 24 | Aug 05 04:22:09 PM PDT 24 | 4766095 ps | ||
| T19 | /workspace/coverage/default/19.prim_esc_test.1194721868 | Aug 05 04:18:40 PM PDT 24 | Aug 05 04:18:40 PM PDT 24 | 5074458 ps | ||
| T20 | /workspace/coverage/default/11.prim_esc_test.3191547383 | Aug 05 04:21:56 PM PDT 24 | Aug 05 04:21:57 PM PDT 24 | 5022245 ps |
| Test location | /workspace/coverage/default/9.prim_esc_test.1143982989 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5307024 ps |
| CPU time | 0.49 seconds |
| Started | Aug 05 04:21:46 PM PDT 24 |
| Finished | Aug 05 04:21:47 PM PDT 24 |
| Peak memory | 145404 kb |
| Host | smart-f6ec3221-0d95-421b-8c16-257287053ea6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1143982989 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1143982989 |
| Directory | /workspace/9.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1040990253 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4607075 ps |
| CPU time | 0.37 seconds |
| Started | Aug 05 04:22:54 PM PDT 24 |
| Finished | Aug 05 04:22:54 PM PDT 24 |
| Peak memory | 147088 kb |
| Host | smart-ecbf2d46-8973-4769-a176-521e64690d88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1040990253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1040990253 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2183905978 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4327215 ps |
| CPU time | 0.38 seconds |
| Started | Aug 05 04:19:28 PM PDT 24 |
| Finished | Aug 05 04:19:29 PM PDT 24 |
| Peak memory | 146336 kb |
| Host | smart-42d68e4a-151d-4ba7-9d32-986e013a3833 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2183905978 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2183905978 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.2424809129 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4818828 ps |
| CPU time | 0.39 seconds |
| Started | Aug 05 04:21:49 PM PDT 24 |
| Finished | Aug 05 04:21:50 PM PDT 24 |
| Peak memory | 146704 kb |
| Host | smart-2dafad86-3f6c-405c-bc6a-b4481c566320 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424809129 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2424809129 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3180421569 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5053098 ps |
| CPU time | 0.37 seconds |
| Started | Aug 05 04:21:55 PM PDT 24 |
| Finished | Aug 05 04:21:56 PM PDT 24 |
| Peak memory | 146304 kb |
| Host | smart-992b1e45-a083-425a-b6a5-dd276d4ace1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180421569 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3180421569 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3082973121 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4852578 ps |
| CPU time | 0.37 seconds |
| Started | Aug 05 04:21:53 PM PDT 24 |
| Finished | Aug 05 04:21:54 PM PDT 24 |
| Peak memory | 146260 kb |
| Host | smart-8da5a451-0796-425c-9f3a-d977cc71b7b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3082973121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3082973121 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3191547383 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5022245 ps |
| CPU time | 0.38 seconds |
| Started | Aug 05 04:21:56 PM PDT 24 |
| Finished | Aug 05 04:21:57 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-83c5f92a-8043-4015-896e-d1a967380772 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3191547383 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3191547383 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3428942143 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5328194 ps |
| CPU time | 0.39 seconds |
| Started | Aug 05 04:21:56 PM PDT 24 |
| Finished | Aug 05 04:21:56 PM PDT 24 |
| Peak memory | 146324 kb |
| Host | smart-c961f9c6-205e-470c-9e43-15933cce55a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3428942143 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3428942143 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.4045329312 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4894606 ps |
| CPU time | 0.39 seconds |
| Started | Aug 05 04:20:26 PM PDT 24 |
| Finished | Aug 05 04:20:26 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-63e99219-22e3-4d91-af21-af30beb55947 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4045329312 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4045329312 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.207073830 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4805567 ps |
| CPU time | 0.39 seconds |
| Started | Aug 05 04:22:11 PM PDT 24 |
| Finished | Aug 05 04:22:12 PM PDT 24 |
| Peak memory | 145904 kb |
| Host | smart-7c505431-d8a6-4053-970d-d39c2fc0f3b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=207073830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.207073830 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2475841824 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5071174 ps |
| CPU time | 0.39 seconds |
| Started | Aug 05 04:22:53 PM PDT 24 |
| Finished | Aug 05 04:22:54 PM PDT 24 |
| Peak memory | 147056 kb |
| Host | smart-18723127-830e-4f86-936a-0605220c3d17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2475841824 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2475841824 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3844619620 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4809626 ps |
| CPU time | 0.4 seconds |
| Started | Aug 05 04:22:11 PM PDT 24 |
| Finished | Aug 05 04:22:11 PM PDT 24 |
| Peak memory | 146676 kb |
| Host | smart-041f75d2-1be9-4efd-8251-899853d0b7e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3844619620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3844619620 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1194721868 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5074458 ps |
| CPU time | 0.4 seconds |
| Started | Aug 05 04:18:40 PM PDT 24 |
| Finished | Aug 05 04:18:40 PM PDT 24 |
| Peak memory | 146152 kb |
| Host | smart-0b2e5bce-6068-45d8-a925-13793996df4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1194721868 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1194721868 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3111861043 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5296560 ps |
| CPU time | 0.38 seconds |
| Started | Aug 05 04:21:56 PM PDT 24 |
| Finished | Aug 05 04:21:56 PM PDT 24 |
| Peak memory | 146304 kb |
| Host | smart-b24bc3bc-2b8d-4a85-a7a1-d8f757887b86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3111861043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3111861043 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2615035495 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4336197 ps |
| CPU time | 0.39 seconds |
| Started | Aug 05 04:22:24 PM PDT 24 |
| Finished | Aug 05 04:22:25 PM PDT 24 |
| Peak memory | 146312 kb |
| Host | smart-f6de1e2d-c451-48b6-a663-ba6e7eff037f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2615035495 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2615035495 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.179561225 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4831707 ps |
| CPU time | 0.38 seconds |
| Started | Aug 05 04:21:53 PM PDT 24 |
| Finished | Aug 05 04:21:54 PM PDT 24 |
| Peak memory | 146276 kb |
| Host | smart-aead871e-ba7b-40aa-969f-bbbd168a174b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=179561225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.179561225 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1100704616 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5416951 ps |
| CPU time | 0.37 seconds |
| Started | Aug 05 04:21:53 PM PDT 24 |
| Finished | Aug 05 04:21:54 PM PDT 24 |
| Peak memory | 146284 kb |
| Host | smart-3579a315-c4b6-421a-aeae-5573dc0b84ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1100704616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1100704616 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2494093444 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4133410 ps |
| CPU time | 0.37 seconds |
| Started | Aug 05 04:21:56 PM PDT 24 |
| Finished | Aug 05 04:21:56 PM PDT 24 |
| Peak memory | 146304 kb |
| Host | smart-a0cbf2af-cfa0-48b6-8b3a-dc58941cce1b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2494093444 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2494093444 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3257977696 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4766095 ps |
| CPU time | 0.38 seconds |
| Started | Aug 05 04:22:08 PM PDT 24 |
| Finished | Aug 05 04:22:09 PM PDT 24 |
| Peak memory | 145264 kb |
| Host | smart-ed927f88-6dba-4b62-acb2-26a5ef442f55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3257977696 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3257977696 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3540157136 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5474024 ps |
| CPU time | 0.38 seconds |
| Started | Aug 05 04:22:24 PM PDT 24 |
| Finished | Aug 05 04:22:25 PM PDT 24 |
| Peak memory | 146312 kb |
| Host | smart-7da7a8fb-f5ba-472c-8c5b-a7245eeea643 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3540157136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3540157136 |
| Directory | /workspace/8.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |