| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/16.prim_esc_test.673003089 |
| 89.45 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/10.prim_esc_test.267743160 |
| 91.17 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/18.prim_esc_test.879451070 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/6.prim_esc_test.715279841 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2166916835 |
| /workspace/coverage/default/1.prim_esc_test.3036947179 |
| /workspace/coverage/default/11.prim_esc_test.439506800 |
| /workspace/coverage/default/12.prim_esc_test.2315885314 |
| /workspace/coverage/default/13.prim_esc_test.1405155260 |
| /workspace/coverage/default/14.prim_esc_test.761240650 |
| /workspace/coverage/default/15.prim_esc_test.3994318223 |
| /workspace/coverage/default/17.prim_esc_test.4266497665 |
| /workspace/coverage/default/19.prim_esc_test.4074792467 |
| /workspace/coverage/default/2.prim_esc_test.1415662643 |
| /workspace/coverage/default/3.prim_esc_test.1492491006 |
| /workspace/coverage/default/4.prim_esc_test.4180121315 |
| /workspace/coverage/default/5.prim_esc_test.1923784453 |
| /workspace/coverage/default/7.prim_esc_test.2073696357 |
| /workspace/coverage/default/8.prim_esc_test.2923979932 |
| /workspace/coverage/default/9.prim_esc_test.122904729 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/4.prim_esc_test.4180121315 | Aug 06 04:27:45 PM PDT 24 | Aug 06 04:27:45 PM PDT 24 | 4843355 ps | ||
| T2 | /workspace/coverage/default/14.prim_esc_test.761240650 | Aug 06 04:26:59 PM PDT 24 | Aug 06 04:27:00 PM PDT 24 | 5422698 ps | ||
| T3 | /workspace/coverage/default/7.prim_esc_test.2073696357 | Aug 06 04:26:59 PM PDT 24 | Aug 06 04:26:59 PM PDT 24 | 4953156 ps | ||
| T4 | /workspace/coverage/default/10.prim_esc_test.267743160 | Aug 06 04:26:55 PM PDT 24 | Aug 06 04:26:56 PM PDT 24 | 5005964 ps | ||
| T5 | /workspace/coverage/default/8.prim_esc_test.2923979932 | Aug 06 04:27:07 PM PDT 24 | Aug 06 04:27:07 PM PDT 24 | 4768125 ps | ||
| T13 | /workspace/coverage/default/0.prim_esc_test.2166916835 | Aug 06 04:26:40 PM PDT 24 | Aug 06 04:26:41 PM PDT 24 | 4360365 ps | ||
| T6 | /workspace/coverage/default/2.prim_esc_test.1415662643 | Aug 06 04:28:14 PM PDT 24 | Aug 06 04:28:15 PM PDT 24 | 5246152 ps | ||
| T7 | /workspace/coverage/default/16.prim_esc_test.673003089 | Aug 06 04:26:56 PM PDT 24 | Aug 06 04:26:57 PM PDT 24 | 5432488 ps | ||
| T14 | /workspace/coverage/default/17.prim_esc_test.4266497665 | Aug 06 04:26:58 PM PDT 24 | Aug 06 04:26:59 PM PDT 24 | 5340449 ps | ||
| T9 | /workspace/coverage/default/15.prim_esc_test.3994318223 | Aug 06 04:26:54 PM PDT 24 | Aug 06 04:26:55 PM PDT 24 | 4758244 ps | ||
| T11 | /workspace/coverage/default/9.prim_esc_test.122904729 | Aug 06 04:27:07 PM PDT 24 | Aug 06 04:27:08 PM PDT 24 | 5035570 ps | ||
| T10 | /workspace/coverage/default/3.prim_esc_test.1492491006 | Aug 06 04:26:39 PM PDT 24 | Aug 06 04:26:40 PM PDT 24 | 5196068 ps | ||
| T15 | /workspace/coverage/default/11.prim_esc_test.439506800 | Aug 06 04:27:02 PM PDT 24 | Aug 06 04:27:03 PM PDT 24 | 4672212 ps | ||
| T16 | /workspace/coverage/default/1.prim_esc_test.3036947179 | Aug 06 04:27:58 PM PDT 24 | Aug 06 04:27:58 PM PDT 24 | 5136212 ps | ||
| T8 | /workspace/coverage/default/12.prim_esc_test.2315885314 | Aug 06 04:26:57 PM PDT 24 | Aug 06 04:26:57 PM PDT 24 | 5148134 ps | ||
| T17 | /workspace/coverage/default/13.prim_esc_test.1405155260 | Aug 06 04:27:07 PM PDT 24 | Aug 06 04:27:08 PM PDT 24 | 4786007 ps | ||
| T18 | /workspace/coverage/default/18.prim_esc_test.879451070 | Aug 06 04:27:01 PM PDT 24 | Aug 06 04:27:01 PM PDT 24 | 4905976 ps | ||
| T19 | /workspace/coverage/default/19.prim_esc_test.4074792467 | Aug 06 04:26:55 PM PDT 24 | Aug 06 04:26:56 PM PDT 24 | 4171376 ps | ||
| T12 | /workspace/coverage/default/6.prim_esc_test.715279841 | Aug 06 04:27:58 PM PDT 24 | Aug 06 04:27:58 PM PDT 24 | 4942478 ps | ||
| T20 | /workspace/coverage/default/5.prim_esc_test.1923784453 | Aug 06 04:27:46 PM PDT 24 | Aug 06 04:27:47 PM PDT 24 | 5176181 ps |
| Test location | /workspace/coverage/default/16.prim_esc_test.673003089 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5432488 ps |
| CPU time | 0.38 seconds |
| Started | Aug 06 04:26:56 PM PDT 24 |
| Finished | Aug 06 04:26:57 PM PDT 24 |
| Peak memory | 146312 kb |
| Host | smart-7b2ac213-04e1-442d-8088-b556a1c6fcc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=673003089 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.673003089 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.267743160 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5005964 ps |
| CPU time | 0.38 seconds |
| Started | Aug 06 04:26:55 PM PDT 24 |
| Finished | Aug 06 04:26:56 PM PDT 24 |
| Peak memory | 146032 kb |
| Host | smart-48309e8a-c4e7-428e-b34b-f4e645a385ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267743160 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.267743160 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.879451070 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4905976 ps |
| CPU time | 0.39 seconds |
| Started | Aug 06 04:27:01 PM PDT 24 |
| Finished | Aug 06 04:27:01 PM PDT 24 |
| Peak memory | 146272 kb |
| Host | smart-f9ae2872-9675-4a6a-8c57-0d4dc6d00187 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=879451070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.879451070 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.715279841 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4942478 ps |
| CPU time | 0.42 seconds |
| Started | Aug 06 04:27:58 PM PDT 24 |
| Finished | Aug 06 04:27:58 PM PDT 24 |
| Peak memory | 146080 kb |
| Host | smart-6b12064e-191d-49e1-8dd7-0d504e2cafc0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=715279841 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.715279841 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2166916835 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4360365 ps |
| CPU time | 0.38 seconds |
| Started | Aug 06 04:26:40 PM PDT 24 |
| Finished | Aug 06 04:26:41 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-9335c76a-f976-4029-909f-1d11fdaf7125 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2166916835 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2166916835 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3036947179 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5136212 ps |
| CPU time | 0.42 seconds |
| Started | Aug 06 04:27:58 PM PDT 24 |
| Finished | Aug 06 04:27:58 PM PDT 24 |
| Peak memory | 145108 kb |
| Host | smart-2cc3cfd4-f1f7-4feb-a65e-8caf85eaf27c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3036947179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3036947179 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.439506800 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4672212 ps |
| CPU time | 0.39 seconds |
| Started | Aug 06 04:27:02 PM PDT 24 |
| Finished | Aug 06 04:27:03 PM PDT 24 |
| Peak memory | 146084 kb |
| Host | smart-becf0bf3-4a0a-46bf-a352-1960d3faa134 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=439506800 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.439506800 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2315885314 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5148134 ps |
| CPU time | 0.37 seconds |
| Started | Aug 06 04:26:57 PM PDT 24 |
| Finished | Aug 06 04:26:57 PM PDT 24 |
| Peak memory | 146084 kb |
| Host | smart-726e8cb8-e7c8-429e-8247-41b6b69e1d90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2315885314 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2315885314 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1405155260 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4786007 ps |
| CPU time | 0.39 seconds |
| Started | Aug 06 04:27:07 PM PDT 24 |
| Finished | Aug 06 04:27:08 PM PDT 24 |
| Peak memory | 146312 kb |
| Host | smart-8ee128f1-b0b1-49c0-a99b-f347e61b3bd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1405155260 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1405155260 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.761240650 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5422698 ps |
| CPU time | 0.37 seconds |
| Started | Aug 06 04:26:59 PM PDT 24 |
| Finished | Aug 06 04:27:00 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-e900876b-4435-4d65-8c9f-7b8996623251 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=761240650 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.761240650 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3994318223 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4758244 ps |
| CPU time | 0.39 seconds |
| Started | Aug 06 04:26:54 PM PDT 24 |
| Finished | Aug 06 04:26:55 PM PDT 24 |
| Peak memory | 146312 kb |
| Host | smart-691f72ca-baa1-422d-bb47-82fa1832e30a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3994318223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3994318223 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.4266497665 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5340449 ps |
| CPU time | 0.37 seconds |
| Started | Aug 06 04:26:58 PM PDT 24 |
| Finished | Aug 06 04:26:59 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-d0325961-d71d-4e06-bbff-583de9d7db1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4266497665 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.4266497665 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.4074792467 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4171376 ps |
| CPU time | 0.39 seconds |
| Started | Aug 06 04:26:55 PM PDT 24 |
| Finished | Aug 06 04:26:56 PM PDT 24 |
| Peak memory | 146284 kb |
| Host | smart-67ec907d-a8f3-4d95-8ca9-acb0eb07d2d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4074792467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.4074792467 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1415662643 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5246152 ps |
| CPU time | 0.37 seconds |
| Started | Aug 06 04:28:14 PM PDT 24 |
| Finished | Aug 06 04:28:15 PM PDT 24 |
| Peak memory | 146280 kb |
| Host | smart-18c83f6a-3142-45a1-8c80-f6ed853a9f77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415662643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1415662643 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1492491006 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5196068 ps |
| CPU time | 0.39 seconds |
| Started | Aug 06 04:26:39 PM PDT 24 |
| Finished | Aug 06 04:26:40 PM PDT 24 |
| Peak memory | 146432 kb |
| Host | smart-7275a1f3-cba5-4dba-b3cb-fed95f71a670 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1492491006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1492491006 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.4180121315 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4843355 ps |
| CPU time | 0.45 seconds |
| Started | Aug 06 04:27:45 PM PDT 24 |
| Finished | Aug 06 04:27:45 PM PDT 24 |
| Peak memory | 146660 kb |
| Host | smart-2ec276c9-a517-4588-90bd-ebe5b224ee85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180121315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.4180121315 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1923784453 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5176181 ps |
| CPU time | 0.38 seconds |
| Started | Aug 06 04:27:46 PM PDT 24 |
| Finished | Aug 06 04:27:47 PM PDT 24 |
| Peak memory | 146140 kb |
| Host | smart-1bceacb4-5d9f-4458-8413-32af7ac35b7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1923784453 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1923784453 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.2073696357 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4953156 ps |
| CPU time | 0.39 seconds |
| Started | Aug 06 04:26:59 PM PDT 24 |
| Finished | Aug 06 04:26:59 PM PDT 24 |
| Peak memory | 146328 kb |
| Host | smart-cb136fd9-380f-428f-9ac0-97ac0e9d832e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2073696357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2073696357 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.2923979932 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4768125 ps |
| CPU time | 0.37 seconds |
| Started | Aug 06 04:27:07 PM PDT 24 |
| Finished | Aug 06 04:27:07 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-99e95eb6-dccd-411f-9835-36f2b61defce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2923979932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.2923979932 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.122904729 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5035570 ps |
| CPU time | 0.38 seconds |
| Started | Aug 06 04:27:07 PM PDT 24 |
| Finished | Aug 06 04:27:08 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-f434d154-0506-4b64-9a36-4917840b0be1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=122904729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.122904729 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |