| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.74 | 87.74 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 78.57 | 78.57 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/18.prim_esc_test.1703803283 |
| 90.05 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/17.prim_esc_test.493538420 |
| 91.17 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/0.prim_esc_test.1335540460 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/2.prim_esc_test.3817523178 |
| Name |
|---|
| /workspace/coverage/default/1.prim_esc_test.1252186680 |
| /workspace/coverage/default/10.prim_esc_test.1429679932 |
| /workspace/coverage/default/11.prim_esc_test.2828790740 |
| /workspace/coverage/default/12.prim_esc_test.2973460942 |
| /workspace/coverage/default/13.prim_esc_test.2785912948 |
| /workspace/coverage/default/14.prim_esc_test.1968178598 |
| /workspace/coverage/default/15.prim_esc_test.2604401481 |
| /workspace/coverage/default/16.prim_esc_test.1241061137 |
| /workspace/coverage/default/19.prim_esc_test.1364229700 |
| /workspace/coverage/default/3.prim_esc_test.3471813056 |
| /workspace/coverage/default/4.prim_esc_test.1876942322 |
| /workspace/coverage/default/5.prim_esc_test.3372195745 |
| /workspace/coverage/default/6.prim_esc_test.2716997657 |
| /workspace/coverage/default/7.prim_esc_test.2275168500 |
| /workspace/coverage/default/8.prim_esc_test.3755755862 |
| /workspace/coverage/default/9.prim_esc_test.1963389155 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/1.prim_esc_test.1252186680 | Aug 07 04:25:26 PM PDT 24 | Aug 07 04:25:27 PM PDT 24 | 5239793 ps | ||
| T2 | /workspace/coverage/default/6.prim_esc_test.2716997657 | Aug 07 04:24:47 PM PDT 24 | Aug 07 04:24:47 PM PDT 24 | 5383095 ps | ||
| T3 | /workspace/coverage/default/16.prim_esc_test.1241061137 | Aug 07 04:21:38 PM PDT 24 | Aug 07 04:21:38 PM PDT 24 | 4661754 ps | ||
| T4 | /workspace/coverage/default/18.prim_esc_test.1703803283 | Aug 07 04:24:31 PM PDT 24 | Aug 07 04:24:32 PM PDT 24 | 4847863 ps | ||
| T5 | /workspace/coverage/default/12.prim_esc_test.2973460942 | Aug 07 04:20:49 PM PDT 24 | Aug 07 04:20:50 PM PDT 24 | 5194106 ps | ||
| T6 | /workspace/coverage/default/4.prim_esc_test.1876942322 | Aug 07 04:24:33 PM PDT 24 | Aug 07 04:24:34 PM PDT 24 | 4747856 ps | ||
| T14 | /workspace/coverage/default/15.prim_esc_test.2604401481 | Aug 07 04:21:16 PM PDT 24 | Aug 07 04:21:17 PM PDT 24 | 4584831 ps | ||
| T10 | /workspace/coverage/default/0.prim_esc_test.1335540460 | Aug 07 04:20:34 PM PDT 24 | Aug 07 04:20:34 PM PDT 24 | 4575360 ps | ||
| T7 | /workspace/coverage/default/10.prim_esc_test.1429679932 | Aug 07 04:20:43 PM PDT 24 | Aug 07 04:20:43 PM PDT 24 | 4899404 ps | ||
| T11 | /workspace/coverage/default/7.prim_esc_test.2275168500 | Aug 07 04:22:53 PM PDT 24 | Aug 07 04:22:53 PM PDT 24 | 4541949 ps | ||
| T12 | /workspace/coverage/default/8.prim_esc_test.3755755862 | Aug 07 04:20:42 PM PDT 24 | Aug 07 04:20:43 PM PDT 24 | 4851844 ps | ||
| T13 | /workspace/coverage/default/9.prim_esc_test.1963389155 | Aug 07 04:22:09 PM PDT 24 | Aug 07 04:22:10 PM PDT 24 | 4624240 ps | ||
| T9 | /workspace/coverage/default/11.prim_esc_test.2828790740 | Aug 07 04:22:28 PM PDT 24 | Aug 07 04:22:28 PM PDT 24 | 5595623 ps | ||
| T8 | /workspace/coverage/default/17.prim_esc_test.493538420 | Aug 07 04:20:44 PM PDT 24 | Aug 07 04:20:44 PM PDT 24 | 4696391 ps | ||
| T15 | /workspace/coverage/default/14.prim_esc_test.1968178598 | Aug 07 04:24:48 PM PDT 24 | Aug 07 04:24:48 PM PDT 24 | 5146660 ps | ||
| T16 | /workspace/coverage/default/19.prim_esc_test.1364229700 | Aug 07 04:21:08 PM PDT 24 | Aug 07 04:21:09 PM PDT 24 | 4740330 ps | ||
| T17 | /workspace/coverage/default/13.prim_esc_test.2785912948 | Aug 07 04:23:12 PM PDT 24 | Aug 07 04:23:13 PM PDT 24 | 4658916 ps | ||
| T18 | /workspace/coverage/default/2.prim_esc_test.3817523178 | Aug 07 04:20:32 PM PDT 24 | Aug 07 04:20:33 PM PDT 24 | 4962959 ps | ||
| T19 | /workspace/coverage/default/3.prim_esc_test.3471813056 | Aug 07 04:20:16 PM PDT 24 | Aug 07 04:20:16 PM PDT 24 | 4664478 ps | ||
| T20 | /workspace/coverage/default/5.prim_esc_test.3372195745 | Aug 07 04:21:59 PM PDT 24 | Aug 07 04:21:59 PM PDT 24 | 4685587 ps |
| Test location | /workspace/coverage/default/18.prim_esc_test.1703803283 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4847863 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:24:31 PM PDT 24 |
| Finished | Aug 07 04:24:32 PM PDT 24 |
| Peak memory | 146696 kb |
| Host | smart-48383fa0-6aaa-4a73-9db8-3c2c54133613 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1703803283 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1703803283 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.493538420 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4696391 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:20:44 PM PDT 24 |
| Finished | Aug 07 04:20:44 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-07edaa54-2576-4918-8929-eba07f755efc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=493538420 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.493538420 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1335540460 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4575360 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:20:34 PM PDT 24 |
| Finished | Aug 07 04:20:34 PM PDT 24 |
| Peak memory | 146344 kb |
| Host | smart-de04d8f8-6ab3-435f-bf3d-8fb05c22fc88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1335540460 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1335540460 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3817523178 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4962959 ps |
| CPU time | 0.42 seconds |
| Started | Aug 07 04:20:32 PM PDT 24 |
| Finished | Aug 07 04:20:33 PM PDT 24 |
| Peak memory | 146652 kb |
| Host | smart-db415241-e253-4019-a887-361b3f9d8f0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3817523178 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3817523178 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.1252186680 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5239793 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:25:26 PM PDT 24 |
| Finished | Aug 07 04:25:27 PM PDT 24 |
| Peak memory | 146472 kb |
| Host | smart-df331180-23ff-432c-beec-96b5ee163de4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1252186680 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1252186680 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1429679932 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4899404 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:20:43 PM PDT 24 |
| Finished | Aug 07 04:20:43 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-db61ae52-d002-4dd4-8586-718f3e9688f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1429679932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1429679932 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2828790740 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5595623 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:22:28 PM PDT 24 |
| Finished | Aug 07 04:22:28 PM PDT 24 |
| Peak memory | 146312 kb |
| Host | smart-4f594a90-1a00-47a7-9635-5af15d945060 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828790740 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2828790740 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2973460942 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5194106 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:20:49 PM PDT 24 |
| Finished | Aug 07 04:20:50 PM PDT 24 |
| Peak memory | 146380 kb |
| Host | smart-6a42e924-019f-48a1-b271-4cecbc65649b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2973460942 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2973460942 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2785912948 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4658916 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:23:12 PM PDT 24 |
| Finished | Aug 07 04:23:13 PM PDT 24 |
| Peak memory | 146388 kb |
| Host | smart-d6be6662-afe7-404e-a3af-33957573a4ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2785912948 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2785912948 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1968178598 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5146660 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:24:48 PM PDT 24 |
| Finished | Aug 07 04:24:48 PM PDT 24 |
| Peak memory | 146100 kb |
| Host | smart-2f1dc445-46bf-4b58-9fb1-198ae161db9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1968178598 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1968178598 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.2604401481 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4584831 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:21:16 PM PDT 24 |
| Finished | Aug 07 04:21:17 PM PDT 24 |
| Peak memory | 146396 kb |
| Host | smart-f371471d-01ec-4941-b190-1f430442f550 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2604401481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2604401481 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1241061137 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4661754 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:21:38 PM PDT 24 |
| Finished | Aug 07 04:21:38 PM PDT 24 |
| Peak memory | 146388 kb |
| Host | smart-8ef7c401-8c26-4c97-ba86-195c4607d419 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1241061137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1241061137 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.1364229700 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4740330 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:21:08 PM PDT 24 |
| Finished | Aug 07 04:21:09 PM PDT 24 |
| Peak memory | 146364 kb |
| Host | smart-3965853a-8701-43ff-bc08-4a215dca9c96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1364229700 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1364229700 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3471813056 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4664478 ps |
| CPU time | 0.41 seconds |
| Started | Aug 07 04:20:16 PM PDT 24 |
| Finished | Aug 07 04:20:16 PM PDT 24 |
| Peak memory | 146652 kb |
| Host | smart-86beb774-6217-4f39-9c81-28207acb8fb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3471813056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3471813056 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1876942322 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4747856 ps |
| CPU time | 0.41 seconds |
| Started | Aug 07 04:24:33 PM PDT 24 |
| Finished | Aug 07 04:24:34 PM PDT 24 |
| Peak memory | 146692 kb |
| Host | smart-c9123dc9-1edc-4ccc-afe0-3b7d7daae43b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1876942322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1876942322 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3372195745 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4685587 ps |
| CPU time | 0.4 seconds |
| Started | Aug 07 04:21:59 PM PDT 24 |
| Finished | Aug 07 04:21:59 PM PDT 24 |
| Peak memory | 146396 kb |
| Host | smart-a2428622-44e1-4da0-8f5b-e0fa3d2a5f4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3372195745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3372195745 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2716997657 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5383095 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:24:47 PM PDT 24 |
| Finished | Aug 07 04:24:47 PM PDT 24 |
| Peak memory | 146104 kb |
| Host | smart-bf0d3113-47a0-404f-ae09-2b083b23ed55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2716997657 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2716997657 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.2275168500 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4541949 ps |
| CPU time | 0.38 seconds |
| Started | Aug 07 04:22:53 PM PDT 24 |
| Finished | Aug 07 04:22:53 PM PDT 24 |
| Peak memory | 146400 kb |
| Host | smart-c61fba3a-5373-48e4-9949-7e6df0262ba9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2275168500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.2275168500 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3755755862 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4851844 ps |
| CPU time | 0.37 seconds |
| Started | Aug 07 04:20:42 PM PDT 24 |
| Finished | Aug 07 04:20:43 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-fe5e1d4c-1e7f-4291-b6ac-65220b2b5a99 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3755755862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3755755862 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1963389155 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4624240 ps |
| CPU time | 0.39 seconds |
| Started | Aug 07 04:22:09 PM PDT 24 |
| Finished | Aug 07 04:22:10 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-b09bba4d-83da-4621-b8e0-02de4ead84d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963389155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1963389155 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |