Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.29 95.41 87.80 100.00 96.43 88.89 85.19


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.74 87.74 92.66 92.66 87.80 87.80 100.00 100.00 78.57 78.57 82.22 82.22 85.19 85.19 /workspace/coverage/default/18.prim_esc_test.2887491573
90.05 2.31 93.58 0.92 87.80 0.00 100.00 0.00 89.29 10.71 84.44 2.22 85.19 0.00 /workspace/coverage/default/8.prim_esc_test.813436836
91.17 1.12 94.50 0.92 87.80 0.00 100.00 0.00 92.86 3.57 86.67 2.22 85.19 0.00 /workspace/coverage/default/0.prim_esc_test.2001869822
92.29 1.12 95.41 0.92 87.80 0.00 100.00 0.00 96.43 3.57 88.89 2.22 85.19 0.00 /workspace/coverage/default/11.prim_esc_test.2864713375

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.1366666394
/workspace/coverage/default/10.prim_esc_test.453433093
/workspace/coverage/default/12.prim_esc_test.113356500
/workspace/coverage/default/13.prim_esc_test.1825592481
/workspace/coverage/default/14.prim_esc_test.3462132230
/workspace/coverage/default/15.prim_esc_test.201483204
/workspace/coverage/default/16.prim_esc_test.2826134244
/workspace/coverage/default/17.prim_esc_test.2382162709
/workspace/coverage/default/19.prim_esc_test.3316285814
/workspace/coverage/default/2.prim_esc_test.3486876878
/workspace/coverage/default/3.prim_esc_test.4191828758
/workspace/coverage/default/4.prim_esc_test.3769236959
/workspace/coverage/default/5.prim_esc_test.606644898
/workspace/coverage/default/6.prim_esc_test.1561277427
/workspace/coverage/default/7.prim_esc_test.1977621674
/workspace/coverage/default/9.prim_esc_test.1881826155



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/8.prim_esc_test.813436836 Aug 08 05:09:30 PM PDT 24 Aug 08 05:09:31 PM PDT 24 5047484 ps
T2 /workspace/coverage/default/7.prim_esc_test.1977621674 Aug 08 05:09:23 PM PDT 24 Aug 08 05:09:23 PM PDT 24 5117655 ps
T3 /workspace/coverage/default/0.prim_esc_test.2001869822 Aug 08 05:09:01 PM PDT 24 Aug 08 05:09:09 PM PDT 24 4334532 ps
T5 /workspace/coverage/default/13.prim_esc_test.1825592481 Aug 08 05:09:11 PM PDT 24 Aug 08 05:09:11 PM PDT 24 4679080 ps
T13 /workspace/coverage/default/6.prim_esc_test.1561277427 Aug 08 05:09:01 PM PDT 24 Aug 08 05:09:01 PM PDT 24 4947914 ps
T4 /workspace/coverage/default/3.prim_esc_test.4191828758 Aug 08 05:09:17 PM PDT 24 Aug 08 05:09:18 PM PDT 24 4940715 ps
T11 /workspace/coverage/default/11.prim_esc_test.2864713375 Aug 08 05:09:16 PM PDT 24 Aug 08 05:09:17 PM PDT 24 4951403 ps
T6 /workspace/coverage/default/18.prim_esc_test.2887491573 Aug 08 05:09:30 PM PDT 24 Aug 08 05:09:30 PM PDT 24 5091050 ps
T14 /workspace/coverage/default/9.prim_esc_test.1881826155 Aug 08 05:09:04 PM PDT 24 Aug 08 05:09:04 PM PDT 24 4386791 ps
T15 /workspace/coverage/default/2.prim_esc_test.3486876878 Aug 08 05:09:04 PM PDT 24 Aug 08 05:09:09 PM PDT 24 5172873 ps
T9 /workspace/coverage/default/5.prim_esc_test.606644898 Aug 08 05:09:05 PM PDT 24 Aug 08 05:09:05 PM PDT 24 4537872 ps
T18 /workspace/coverage/default/14.prim_esc_test.3462132230 Aug 08 05:09:13 PM PDT 24 Aug 08 05:09:13 PM PDT 24 4068927 ps
T19 /workspace/coverage/default/12.prim_esc_test.113356500 Aug 08 05:09:19 PM PDT 24 Aug 08 05:09:20 PM PDT 24 5582710 ps
T16 /workspace/coverage/default/10.prim_esc_test.453433093 Aug 08 05:08:58 PM PDT 24 Aug 08 05:08:59 PM PDT 24 4892469 ps
T10 /workspace/coverage/default/15.prim_esc_test.201483204 Aug 08 05:09:18 PM PDT 24 Aug 08 05:09:18 PM PDT 24 5125108 ps
T17 /workspace/coverage/default/19.prim_esc_test.3316285814 Aug 08 05:09:10 PM PDT 24 Aug 08 05:09:10 PM PDT 24 4474955 ps
T12 /workspace/coverage/default/16.prim_esc_test.2826134244 Aug 08 05:09:12 PM PDT 24 Aug 08 05:09:13 PM PDT 24 5428113 ps
T20 /workspace/coverage/default/17.prim_esc_test.2382162709 Aug 08 05:09:23 PM PDT 24 Aug 08 05:09:23 PM PDT 24 5050113 ps
T8 /workspace/coverage/default/4.prim_esc_test.3769236959 Aug 08 05:09:02 PM PDT 24 Aug 08 05:09:03 PM PDT 24 5261634 ps
T7 /workspace/coverage/default/1.prim_esc_test.1366666394 Aug 08 05:09:11 PM PDT 24 Aug 08 05:09:11 PM PDT 24 4537561 ps

Test location /workspace/coverage/default/18.prim_esc_test.2887491573
Short name T6
Test name
Test status
Simulation time 5091050 ps
CPU time 0.39 seconds
Started Aug 08 05:09:30 PM PDT 24
Finished Aug 08 05:09:30 PM PDT 24
Peak memory 146424 kb
Host smart-1aa8d63b-dd65-45db-b5fb-67bd1831dcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887491573 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.2887491573
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.813436836
Short name T1
Test name
Test status
Simulation time 5047484 ps
CPU time 0.37 seconds
Started Aug 08 05:09:30 PM PDT 24
Finished Aug 08 05:09:31 PM PDT 24
Peak memory 146364 kb
Host smart-ef5988c3-8ff0-47c1-8f61-cdb1c70fddc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813436836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.813436836
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.2001869822
Short name T3
Test name
Test status
Simulation time 4334532 ps
CPU time 0.38 seconds
Started Aug 08 05:09:01 PM PDT 24
Finished Aug 08 05:09:09 PM PDT 24
Peak memory 146428 kb
Host smart-4cb5bafc-c600-464e-90e8-93528acc0fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001869822 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2001869822
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.2864713375
Short name T11
Test name
Test status
Simulation time 4951403 ps
CPU time 0.36 seconds
Started Aug 08 05:09:16 PM PDT 24
Finished Aug 08 05:09:17 PM PDT 24
Peak memory 146484 kb
Host smart-25a7a8d0-9409-4042-9cd6-7cefa1d62c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864713375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2864713375
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.1366666394
Short name T7
Test name
Test status
Simulation time 4537561 ps
CPU time 0.38 seconds
Started Aug 08 05:09:11 PM PDT 24
Finished Aug 08 05:09:11 PM PDT 24
Peak memory 146284 kb
Host smart-707f6cd4-10c0-4fd3-83eb-c18885d9392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366666394 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1366666394
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.453433093
Short name T16
Test name
Test status
Simulation time 4892469 ps
CPU time 0.36 seconds
Started Aug 08 05:08:58 PM PDT 24
Finished Aug 08 05:08:59 PM PDT 24
Peak memory 146476 kb
Host smart-5acb5e19-5573-4bc6-8814-714290452b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453433093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.453433093
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.113356500
Short name T19
Test name
Test status
Simulation time 5582710 ps
CPU time 0.38 seconds
Started Aug 08 05:09:19 PM PDT 24
Finished Aug 08 05:09:20 PM PDT 24
Peak memory 146488 kb
Host smart-863e2af0-3ab6-425b-9a3f-64bb9b2d0212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113356500 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.113356500
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.1825592481
Short name T5
Test name
Test status
Simulation time 4679080 ps
CPU time 0.37 seconds
Started Aug 08 05:09:11 PM PDT 24
Finished Aug 08 05:09:11 PM PDT 24
Peak memory 146352 kb
Host smart-5ea79f48-2587-4717-830a-59e70ce41da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825592481 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1825592481
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.3462132230
Short name T18
Test name
Test status
Simulation time 4068927 ps
CPU time 0.39 seconds
Started Aug 08 05:09:13 PM PDT 24
Finished Aug 08 05:09:13 PM PDT 24
Peak memory 146476 kb
Host smart-8d41d781-b9b6-49c9-abb7-067db2fc072b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462132230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3462132230
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.201483204
Short name T10
Test name
Test status
Simulation time 5125108 ps
CPU time 0.41 seconds
Started Aug 08 05:09:18 PM PDT 24
Finished Aug 08 05:09:18 PM PDT 24
Peak memory 146400 kb
Host smart-8e9198ed-4686-4850-a477-576ff6da4af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201483204 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.201483204
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.2826134244
Short name T12
Test name
Test status
Simulation time 5428113 ps
CPU time 0.38 seconds
Started Aug 08 05:09:12 PM PDT 24
Finished Aug 08 05:09:13 PM PDT 24
Peak memory 146448 kb
Host smart-b1590439-3fda-476c-8865-30efe90f4a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826134244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2826134244
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.2382162709
Short name T20
Test name
Test status
Simulation time 5050113 ps
CPU time 0.38 seconds
Started Aug 08 05:09:23 PM PDT 24
Finished Aug 08 05:09:23 PM PDT 24
Peak memory 146464 kb
Host smart-489968b7-deea-4387-ba80-2e6a3481d4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382162709 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2382162709
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.3316285814
Short name T17
Test name
Test status
Simulation time 4474955 ps
CPU time 0.38 seconds
Started Aug 08 05:09:10 PM PDT 24
Finished Aug 08 05:09:10 PM PDT 24
Peak memory 146484 kb
Host smart-fd8b88d0-b54b-4f52-b1f4-3ce39b671710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316285814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3316285814
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.3486876878
Short name T15
Test name
Test status
Simulation time 5172873 ps
CPU time 0.39 seconds
Started Aug 08 05:09:04 PM PDT 24
Finished Aug 08 05:09:09 PM PDT 24
Peak memory 146400 kb
Host smart-0b30d908-d904-4f9e-b21a-24f3c655293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486876878 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3486876878
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.4191828758
Short name T4
Test name
Test status
Simulation time 4940715 ps
CPU time 0.36 seconds
Started Aug 08 05:09:17 PM PDT 24
Finished Aug 08 05:09:18 PM PDT 24
Peak memory 146364 kb
Host smart-0f20c3cc-ef30-43e5-82fb-735ad9021863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191828758 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.4191828758
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.3769236959
Short name T8
Test name
Test status
Simulation time 5261634 ps
CPU time 0.38 seconds
Started Aug 08 05:09:02 PM PDT 24
Finished Aug 08 05:09:03 PM PDT 24
Peak memory 146428 kb
Host smart-8df79093-1a67-4b85-b10b-b903528b8cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769236959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3769236959
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.606644898
Short name T9
Test name
Test status
Simulation time 4537872 ps
CPU time 0.38 seconds
Started Aug 08 05:09:05 PM PDT 24
Finished Aug 08 05:09:05 PM PDT 24
Peak memory 146412 kb
Host smart-1afa8949-c961-40fb-9db7-c517e69cc78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606644898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.606644898
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.1561277427
Short name T13
Test name
Test status
Simulation time 4947914 ps
CPU time 0.39 seconds
Started Aug 08 05:09:01 PM PDT 24
Finished Aug 08 05:09:01 PM PDT 24
Peak memory 146428 kb
Host smart-e83a8478-caf1-46d1-9dad-f70244d207ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561277427 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1561277427
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.1977621674
Short name T2
Test name
Test status
Simulation time 5117655 ps
CPU time 0.37 seconds
Started Aug 08 05:09:23 PM PDT 24
Finished Aug 08 05:09:23 PM PDT 24
Peak memory 146440 kb
Host smart-f531c9a5-4304-47c5-83ce-34140c2cf17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977621674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1977621674
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.1881826155
Short name T14
Test name
Test status
Simulation time 4386791 ps
CPU time 0.38 seconds
Started Aug 08 05:09:04 PM PDT 24
Finished Aug 08 05:09:04 PM PDT 24
Peak memory 146552 kb
Host smart-ed9129bd-3bc8-4207-aabb-bb6e10ce70c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881826155 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1881826155
Directory /workspace/9.prim_esc_test/latest
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