| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.06 | 86.06 | 90.83 | 90.83 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 80.00 | 80.00 | 85.19 | 85.19 | /workspace/coverage/default/16.prim_esc_test.3775998445 |
| 88.86 | 2.80 | 93.58 | 2.75 | 87.80 | 2.44 | 100.00 | 0.00 | 82.14 | 7.14 | 84.44 | 4.44 | 85.19 | 0.00 | /workspace/coverage/default/3.prim_esc_test.3273843961 |
| 90.57 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/0.prim_esc_test.1001530633 |
| 92.29 | 1.71 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 7.14 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/1.prim_esc_test.519712737 |
| Name |
|---|
| /workspace/coverage/default/10.prim_esc_test.3025633434 |
| /workspace/coverage/default/11.prim_esc_test.3510373918 |
| /workspace/coverage/default/12.prim_esc_test.2047005165 |
| /workspace/coverage/default/13.prim_esc_test.3522012578 |
| /workspace/coverage/default/14.prim_esc_test.3745949603 |
| /workspace/coverage/default/15.prim_esc_test.4017636845 |
| /workspace/coverage/default/17.prim_esc_test.2348074959 |
| /workspace/coverage/default/18.prim_esc_test.3375663675 |
| /workspace/coverage/default/19.prim_esc_test.3597419817 |
| /workspace/coverage/default/2.prim_esc_test.3952335279 |
| /workspace/coverage/default/4.prim_esc_test.346908146 |
| /workspace/coverage/default/5.prim_esc_test.2281647580 |
| /workspace/coverage/default/6.prim_esc_test.4194245949 |
| /workspace/coverage/default/7.prim_esc_test.865772083 |
| /workspace/coverage/default/8.prim_esc_test.1808015276 |
| /workspace/coverage/default/9.prim_esc_test.3225846102 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/9.prim_esc_test.3225846102 | Aug 09 04:25:09 PM PDT 24 | Aug 09 04:25:10 PM PDT 24 | 4582401 ps | ||
| T2 | /workspace/coverage/default/6.prim_esc_test.4194245949 | Aug 09 04:24:20 PM PDT 24 | Aug 09 04:24:20 PM PDT 24 | 4869378 ps | ||
| T3 | /workspace/coverage/default/5.prim_esc_test.2281647580 | Aug 09 04:25:22 PM PDT 24 | Aug 09 04:25:23 PM PDT 24 | 4808627 ps | ||
| T10 | /workspace/coverage/default/8.prim_esc_test.1808015276 | Aug 09 04:23:35 PM PDT 24 | Aug 09 04:23:35 PM PDT 24 | 4860665 ps | ||
| T4 | /workspace/coverage/default/2.prim_esc_test.3952335279 | Aug 09 04:25:28 PM PDT 24 | Aug 09 04:25:28 PM PDT 24 | 5346517 ps | ||
| T6 | /workspace/coverage/default/15.prim_esc_test.4017636845 | Aug 09 04:20:49 PM PDT 24 | Aug 09 04:20:49 PM PDT 24 | 5022867 ps | ||
| T11 | /workspace/coverage/default/1.prim_esc_test.519712737 | Aug 09 04:22:02 PM PDT 24 | Aug 09 04:22:03 PM PDT 24 | 4667739 ps | ||
| T14 | /workspace/coverage/default/4.prim_esc_test.346908146 | Aug 09 04:20:52 PM PDT 24 | Aug 09 04:20:53 PM PDT 24 | 5491651 ps | ||
| T15 | /workspace/coverage/default/12.prim_esc_test.2047005165 | Aug 09 04:25:45 PM PDT 24 | Aug 09 04:25:45 PM PDT 24 | 4685948 ps | ||
| T5 | /workspace/coverage/default/16.prim_esc_test.3775998445 | Aug 09 04:20:47 PM PDT 24 | Aug 09 04:20:48 PM PDT 24 | 5254047 ps | ||
| T7 | /workspace/coverage/default/0.prim_esc_test.1001530633 | Aug 09 04:25:10 PM PDT 24 | Aug 09 04:25:11 PM PDT 24 | 4659854 ps | ||
| T12 | /workspace/coverage/default/14.prim_esc_test.3745949603 | Aug 09 04:25:21 PM PDT 24 | Aug 09 04:25:21 PM PDT 24 | 4628870 ps | ||
| T8 | /workspace/coverage/default/3.prim_esc_test.3273843961 | Aug 09 04:21:27 PM PDT 24 | Aug 09 04:21:27 PM PDT 24 | 4912988 ps | ||
| T9 | /workspace/coverage/default/10.prim_esc_test.3025633434 | Aug 09 04:23:44 PM PDT 24 | Aug 09 04:23:44 PM PDT 24 | 4599146 ps | ||
| T13 | /workspace/coverage/default/18.prim_esc_test.3375663675 | Aug 09 04:20:48 PM PDT 24 | Aug 09 04:20:48 PM PDT 24 | 5049355 ps | ||
| T16 | /workspace/coverage/default/7.prim_esc_test.865772083 | Aug 09 04:25:28 PM PDT 24 | Aug 09 04:25:29 PM PDT 24 | 5030161 ps | ||
| T17 | /workspace/coverage/default/11.prim_esc_test.3510373918 | Aug 09 04:22:23 PM PDT 24 | Aug 09 04:22:23 PM PDT 24 | 5117555 ps | ||
| T18 | /workspace/coverage/default/19.prim_esc_test.3597419817 | Aug 09 04:25:44 PM PDT 24 | Aug 09 04:25:45 PM PDT 24 | 5583957 ps | ||
| T19 | /workspace/coverage/default/13.prim_esc_test.3522012578 | Aug 09 04:21:30 PM PDT 24 | Aug 09 04:21:30 PM PDT 24 | 4848614 ps | ||
| T20 | /workspace/coverage/default/17.prim_esc_test.2348074959 | Aug 09 04:25:29 PM PDT 24 | Aug 09 04:25:30 PM PDT 24 | 5062705 ps |
| Test location | /workspace/coverage/default/16.prim_esc_test.3775998445 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5254047 ps |
| CPU time | 0.37 seconds |
| Started | Aug 09 04:20:47 PM PDT 24 |
| Finished | Aug 09 04:20:48 PM PDT 24 |
| Peak memory | 146108 kb |
| Host | smart-8f0204a7-b6d0-4ee0-95cb-f2dea4449f67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775998445 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3775998445 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3273843961 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4912988 ps |
| CPU time | 0.41 seconds |
| Started | Aug 09 04:21:27 PM PDT 24 |
| Finished | Aug 09 04:21:27 PM PDT 24 |
| Peak memory | 146632 kb |
| Host | smart-9a0d98d7-6fe2-4c78-8d49-1a616eca6746 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273843961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3273843961 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1001530633 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4659854 ps |
| CPU time | 0.42 seconds |
| Started | Aug 09 04:25:10 PM PDT 24 |
| Finished | Aug 09 04:25:11 PM PDT 24 |
| Peak memory | 146668 kb |
| Host | smart-a3c23b5a-2dbe-4104-8e8b-a99e62402a33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001530633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1001530633 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.519712737 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4667739 ps |
| CPU time | 0.45 seconds |
| Started | Aug 09 04:22:02 PM PDT 24 |
| Finished | Aug 09 04:22:03 PM PDT 24 |
| Peak memory | 146360 kb |
| Host | smart-9ac215b4-4038-4138-9a96-5a2f4352be2a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519712737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.519712737 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3025633434 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4599146 ps |
| CPU time | 0.37 seconds |
| Started | Aug 09 04:23:44 PM PDT 24 |
| Finished | Aug 09 04:23:44 PM PDT 24 |
| Peak memory | 146392 kb |
| Host | smart-adbd9e5e-f15c-458a-8b76-889ed8932157 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3025633434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3025633434 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3510373918 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5117555 ps |
| CPU time | 0.37 seconds |
| Started | Aug 09 04:22:23 PM PDT 24 |
| Finished | Aug 09 04:22:23 PM PDT 24 |
| Peak memory | 146384 kb |
| Host | smart-a4edbf1b-b0e7-41bc-b7e8-cc16c3c5b4da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3510373918 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3510373918 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2047005165 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4685948 ps |
| CPU time | 0.37 seconds |
| Started | Aug 09 04:25:45 PM PDT 24 |
| Finished | Aug 09 04:25:45 PM PDT 24 |
| Peak memory | 146092 kb |
| Host | smart-a7c664ce-9171-43c5-8926-7dcf664f50dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2047005165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2047005165 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.3522012578 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4848614 ps |
| CPU time | 0.39 seconds |
| Started | Aug 09 04:21:30 PM PDT 24 |
| Finished | Aug 09 04:21:30 PM PDT 24 |
| Peak memory | 146364 kb |
| Host | smart-bea0179f-0269-4b52-a2fb-5e1cac0aeeaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3522012578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3522012578 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3745949603 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4628870 ps |
| CPU time | 0.36 seconds |
| Started | Aug 09 04:25:21 PM PDT 24 |
| Finished | Aug 09 04:25:21 PM PDT 24 |
| Peak memory | 146152 kb |
| Host | smart-c5051814-1947-452b-9a0c-ddae8dcafa4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3745949603 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3745949603 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.4017636845 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5022867 ps |
| CPU time | 0.37 seconds |
| Started | Aug 09 04:20:49 PM PDT 24 |
| Finished | Aug 09 04:20:49 PM PDT 24 |
| Peak memory | 146216 kb |
| Host | smart-e4f98377-232d-40c5-b563-efea16179e53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017636845 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.4017636845 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2348074959 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5062705 ps |
| CPU time | 0.36 seconds |
| Started | Aug 09 04:25:29 PM PDT 24 |
| Finished | Aug 09 04:25:30 PM PDT 24 |
| Peak memory | 146068 kb |
| Host | smart-927389ef-2c88-4d60-88ba-dc615338cde5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2348074959 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2348074959 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3375663675 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5049355 ps |
| CPU time | 0.39 seconds |
| Started | Aug 09 04:20:48 PM PDT 24 |
| Finished | Aug 09 04:20:48 PM PDT 24 |
| Peak memory | 146144 kb |
| Host | smart-9cd92bf3-dc8e-4f4c-bcfb-30a15545c35c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3375663675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3375663675 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3597419817 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5583957 ps |
| CPU time | 0.37 seconds |
| Started | Aug 09 04:25:44 PM PDT 24 |
| Finished | Aug 09 04:25:45 PM PDT 24 |
| Peak memory | 146328 kb |
| Host | smart-299d7d14-fbaa-40a0-ba51-64c81a4f75c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3597419817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3597419817 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.3952335279 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5346517 ps |
| CPU time | 0.38 seconds |
| Started | Aug 09 04:25:28 PM PDT 24 |
| Finished | Aug 09 04:25:28 PM PDT 24 |
| Peak memory | 145648 kb |
| Host | smart-91c410f0-7252-4c59-bf62-f4ad2fe939ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3952335279 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3952335279 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.346908146 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5491651 ps |
| CPU time | 0.37 seconds |
| Started | Aug 09 04:20:52 PM PDT 24 |
| Finished | Aug 09 04:20:53 PM PDT 24 |
| Peak memory | 146320 kb |
| Host | smart-bb319de6-7d74-4b12-872a-b97d0264b177 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=346908146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.346908146 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2281647580 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4808627 ps |
| CPU time | 0.36 seconds |
| Started | Aug 09 04:25:22 PM PDT 24 |
| Finished | Aug 09 04:25:23 PM PDT 24 |
| Peak memory | 146340 kb |
| Host | smart-b5177571-5f9d-46df-9157-8fd4d264be08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2281647580 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2281647580 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.4194245949 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4869378 ps |
| CPU time | 0.37 seconds |
| Started | Aug 09 04:24:20 PM PDT 24 |
| Finished | Aug 09 04:24:20 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-65c6b996-21ce-42c6-9f7b-877515c58ec9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194245949 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4194245949 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.865772083 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5030161 ps |
| CPU time | 0.37 seconds |
| Started | Aug 09 04:25:28 PM PDT 24 |
| Finished | Aug 09 04:25:29 PM PDT 24 |
| Peak memory | 146060 kb |
| Host | smart-911bb3e6-b307-4000-b5ca-de184f40dfcf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=865772083 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.865772083 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1808015276 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4860665 ps |
| CPU time | 0.39 seconds |
| Started | Aug 09 04:23:35 PM PDT 24 |
| Finished | Aug 09 04:23:35 PM PDT 24 |
| Peak memory | 146396 kb |
| Host | smart-3923f584-eaf5-4692-9b0b-66b455804c5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1808015276 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1808015276 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3225846102 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4582401 ps |
| CPU time | 0.39 seconds |
| Started | Aug 09 04:25:09 PM PDT 24 |
| Finished | Aug 09 04:25:10 PM PDT 24 |
| Peak memory | 145104 kb |
| Host | smart-60e58034-2cce-4c3a-9573-8fe2ce3d658b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3225846102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3225846102 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |