Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.29 95.41 87.80 100.00 96.43 88.89 85.19


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.66 85.66 90.83 90.83 82.93 82.93 100.00 100.00 75.00 75.00 80.00 80.00 85.19 85.19 /workspace/coverage/default/7.prim_esc_test.162419544
89.05 3.39 93.58 2.75 85.37 2.44 100.00 0.00 85.71 10.71 84.44 4.44 85.19 0.00 /workspace/coverage/default/13.prim_esc_test.1744194375
91.17 2.12 94.50 0.92 87.80 2.44 100.00 0.00 92.86 7.14 86.67 2.22 85.19 0.00 /workspace/coverage/default/9.prim_esc_test.1921159778
92.29 1.12 95.41 0.92 87.80 0.00 100.00 0.00 96.43 3.57 88.89 2.22 85.19 0.00 /workspace/coverage/default/11.prim_esc_test.316353647

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.2287952430
/workspace/coverage/default/1.prim_esc_test.3682834743
/workspace/coverage/default/10.prim_esc_test.3473998496
/workspace/coverage/default/12.prim_esc_test.2169691516
/workspace/coverage/default/14.prim_esc_test.734319239
/workspace/coverage/default/15.prim_esc_test.2579891198
/workspace/coverage/default/16.prim_esc_test.2554931921
/workspace/coverage/default/17.prim_esc_test.2315979034
/workspace/coverage/default/18.prim_esc_test.1032130009
/workspace/coverage/default/19.prim_esc_test.4118906390
/workspace/coverage/default/2.prim_esc_test.3397313431
/workspace/coverage/default/3.prim_esc_test.2797513046
/workspace/coverage/default/4.prim_esc_test.4196538501
/workspace/coverage/default/5.prim_esc_test.404680578
/workspace/coverage/default/6.prim_esc_test.1612205214
/workspace/coverage/default/8.prim_esc_test.3407059668



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/7.prim_esc_test.162419544 Aug 10 05:05:16 PM PDT 24 Aug 10 05:05:16 PM PDT 24 4803445 ps
T2 /workspace/coverage/default/19.prim_esc_test.4118906390 Aug 10 05:05:21 PM PDT 24 Aug 10 05:05:21 PM PDT 24 4551844 ps
T3 /workspace/coverage/default/16.prim_esc_test.2554931921 Aug 10 05:05:12 PM PDT 24 Aug 10 05:05:13 PM PDT 24 4863320 ps
T4 /workspace/coverage/default/11.prim_esc_test.316353647 Aug 10 05:05:19 PM PDT 24 Aug 10 05:05:19 PM PDT 24 5092288 ps
T6 /workspace/coverage/default/9.prim_esc_test.1921159778 Aug 10 05:05:19 PM PDT 24 Aug 10 05:05:19 PM PDT 24 4775881 ps
T5 /workspace/coverage/default/6.prim_esc_test.1612205214 Aug 10 05:05:13 PM PDT 24 Aug 10 05:05:14 PM PDT 24 4815272 ps
T15 /workspace/coverage/default/12.prim_esc_test.2169691516 Aug 10 05:05:13 PM PDT 24 Aug 10 05:05:14 PM PDT 24 4813846 ps
T13 /workspace/coverage/default/1.prim_esc_test.3682834743 Aug 10 05:05:15 PM PDT 24 Aug 10 05:05:16 PM PDT 24 5020525 ps
T16 /workspace/coverage/default/8.prim_esc_test.3407059668 Aug 10 05:05:20 PM PDT 24 Aug 10 05:05:21 PM PDT 24 5408324 ps
T17 /workspace/coverage/default/17.prim_esc_test.2315979034 Aug 10 05:05:14 PM PDT 24 Aug 10 05:05:15 PM PDT 24 5046021 ps
T12 /workspace/coverage/default/5.prim_esc_test.404680578 Aug 10 05:05:13 PM PDT 24 Aug 10 05:05:13 PM PDT 24 5068550 ps
T18 /workspace/coverage/default/0.prim_esc_test.2287952430 Aug 10 05:05:15 PM PDT 24 Aug 10 05:05:15 PM PDT 24 4564513 ps
T7 /workspace/coverage/default/13.prim_esc_test.1744194375 Aug 10 05:05:21 PM PDT 24 Aug 10 05:05:21 PM PDT 24 4356176 ps
T11 /workspace/coverage/default/15.prim_esc_test.2579891198 Aug 10 05:05:11 PM PDT 24 Aug 10 05:05:11 PM PDT 24 4549110 ps
T8 /workspace/coverage/default/4.prim_esc_test.4196538501 Aug 10 05:05:17 PM PDT 24 Aug 10 05:05:17 PM PDT 24 5020487 ps
T9 /workspace/coverage/default/10.prim_esc_test.3473998496 Aug 10 05:05:21 PM PDT 24 Aug 10 05:05:21 PM PDT 24 5147001 ps
T10 /workspace/coverage/default/14.prim_esc_test.734319239 Aug 10 05:05:15 PM PDT 24 Aug 10 05:05:15 PM PDT 24 5177387 ps
T14 /workspace/coverage/default/3.prim_esc_test.2797513046 Aug 10 05:05:14 PM PDT 24 Aug 10 05:05:15 PM PDT 24 4632860 ps
T19 /workspace/coverage/default/2.prim_esc_test.3397313431 Aug 10 05:05:14 PM PDT 24 Aug 10 05:05:15 PM PDT 24 4919568 ps
T20 /workspace/coverage/default/18.prim_esc_test.1032130009 Aug 10 05:05:14 PM PDT 24 Aug 10 05:05:14 PM PDT 24 4947116 ps

Test location /workspace/coverage/default/7.prim_esc_test.162419544
Short name T1
Test name
Test status
Simulation time 4803445 ps
CPU time 0.4 seconds
Started Aug 10 05:05:16 PM PDT 24
Finished Aug 10 05:05:16 PM PDT 24
Peak memory 146548 kb
Host smart-ba7e1f44-89b3-48d3-a8e7-aec9d1ad45c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162419544 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.162419544
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.1744194375
Short name T7
Test name
Test status
Simulation time 4356176 ps
CPU time 0.39 seconds
Started Aug 10 05:05:21 PM PDT 24
Finished Aug 10 05:05:21 PM PDT 24
Peak memory 146460 kb
Host smart-86801c70-71ab-4fad-9f7f-137da78e043a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744194375 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1744194375
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.1921159778
Short name T6
Test name
Test status
Simulation time 4775881 ps
CPU time 0.38 seconds
Started Aug 10 05:05:19 PM PDT 24
Finished Aug 10 05:05:19 PM PDT 24
Peak memory 146516 kb
Host smart-68312c9b-8699-4ee8-8e6c-8ba48aa17703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921159778 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1921159778
Directory /workspace/9.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.316353647
Short name T4
Test name
Test status
Simulation time 5092288 ps
CPU time 0.38 seconds
Started Aug 10 05:05:19 PM PDT 24
Finished Aug 10 05:05:19 PM PDT 24
Peak memory 146512 kb
Host smart-aa3ff19f-a2a5-48a3-8cd3-a614dd210cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316353647 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.316353647
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.2287952430
Short name T18
Test name
Test status
Simulation time 4564513 ps
CPU time 0.4 seconds
Started Aug 10 05:05:15 PM PDT 24
Finished Aug 10 05:05:15 PM PDT 24
Peak memory 146572 kb
Host smart-81d32604-d02b-4002-9d14-c20d9f9f16a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287952430 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2287952430
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.3682834743
Short name T13
Test name
Test status
Simulation time 5020525 ps
CPU time 0.38 seconds
Started Aug 10 05:05:15 PM PDT 24
Finished Aug 10 05:05:16 PM PDT 24
Peak memory 146556 kb
Host smart-9963aee5-89e5-423c-8b37-22c60c5afc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682834743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3682834743
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.3473998496
Short name T9
Test name
Test status
Simulation time 5147001 ps
CPU time 0.38 seconds
Started Aug 10 05:05:21 PM PDT 24
Finished Aug 10 05:05:21 PM PDT 24
Peak memory 146460 kb
Host smart-d674d058-383c-4632-b3b7-0c2d6dd548ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473998496 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3473998496
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.2169691516
Short name T15
Test name
Test status
Simulation time 4813846 ps
CPU time 0.37 seconds
Started Aug 10 05:05:13 PM PDT 24
Finished Aug 10 05:05:14 PM PDT 24
Peak memory 146540 kb
Host smart-025fb73f-c182-4a3c-938d-32b2bc69a016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169691516 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2169691516
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.734319239
Short name T10
Test name
Test status
Simulation time 5177387 ps
CPU time 0.38 seconds
Started Aug 10 05:05:15 PM PDT 24
Finished Aug 10 05:05:15 PM PDT 24
Peak memory 146388 kb
Host smart-229d21fc-ae09-4337-8cdf-922e4e596d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734319239 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.734319239
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.2579891198
Short name T11
Test name
Test status
Simulation time 4549110 ps
CPU time 0.39 seconds
Started Aug 10 05:05:11 PM PDT 24
Finished Aug 10 05:05:11 PM PDT 24
Peak memory 146440 kb
Host smart-33805a21-41a6-4334-aae6-728a17315ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579891198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2579891198
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.2554931921
Short name T3
Test name
Test status
Simulation time 4863320 ps
CPU time 0.39 seconds
Started Aug 10 05:05:12 PM PDT 24
Finished Aug 10 05:05:13 PM PDT 24
Peak memory 146476 kb
Host smart-987f2a70-2fb9-4ea4-a421-8d4a9671a28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554931921 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2554931921
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.2315979034
Short name T17
Test name
Test status
Simulation time 5046021 ps
CPU time 0.38 seconds
Started Aug 10 05:05:14 PM PDT 24
Finished Aug 10 05:05:15 PM PDT 24
Peak memory 146456 kb
Host smart-faf31576-10fa-4398-9ff2-67232bc57916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315979034 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2315979034
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.1032130009
Short name T20
Test name
Test status
Simulation time 4947116 ps
CPU time 0.38 seconds
Started Aug 10 05:05:14 PM PDT 24
Finished Aug 10 05:05:14 PM PDT 24
Peak memory 146492 kb
Host smart-0c2edd9f-5228-42fb-be29-9345a55ab199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032130009 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1032130009
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.4118906390
Short name T2
Test name
Test status
Simulation time 4551844 ps
CPU time 0.38 seconds
Started Aug 10 05:05:21 PM PDT 24
Finished Aug 10 05:05:21 PM PDT 24
Peak memory 146460 kb
Host smart-e7bf7f0f-4933-4908-98e8-6d0a7a28d664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118906390 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.4118906390
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.3397313431
Short name T19
Test name
Test status
Simulation time 4919568 ps
CPU time 0.41 seconds
Started Aug 10 05:05:14 PM PDT 24
Finished Aug 10 05:05:15 PM PDT 24
Peak memory 146492 kb
Host smart-ce70a454-c1ef-42fd-aec0-fd537ee5a024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397313431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3397313431
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.2797513046
Short name T14
Test name
Test status
Simulation time 4632860 ps
CPU time 0.39 seconds
Started Aug 10 05:05:14 PM PDT 24
Finished Aug 10 05:05:15 PM PDT 24
Peak memory 146472 kb
Host smart-553f2557-0c43-4bbe-8ed9-887b9457819b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797513046 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2797513046
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.4196538501
Short name T8
Test name
Test status
Simulation time 5020487 ps
CPU time 0.38 seconds
Started Aug 10 05:05:17 PM PDT 24
Finished Aug 10 05:05:17 PM PDT 24
Peak memory 146548 kb
Host smart-ac838ff9-e0b9-47f1-b229-2ab3081810e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196538501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.4196538501
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.404680578
Short name T12
Test name
Test status
Simulation time 5068550 ps
CPU time 0.38 seconds
Started Aug 10 05:05:13 PM PDT 24
Finished Aug 10 05:05:13 PM PDT 24
Peak memory 146568 kb
Host smart-ff2f035e-742a-487a-acc8-405c10764f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404680578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.404680578
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.1612205214
Short name T5
Test name
Test status
Simulation time 4815272 ps
CPU time 0.39 seconds
Started Aug 10 05:05:13 PM PDT 24
Finished Aug 10 05:05:14 PM PDT 24
Peak memory 146520 kb
Host smart-180aa367-c849-4c4a-bb36-3be125987f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612205214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1612205214
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.3407059668
Short name T16
Test name
Test status
Simulation time 5408324 ps
CPU time 0.38 seconds
Started Aug 10 05:05:20 PM PDT 24
Finished Aug 10 05:05:21 PM PDT 24
Peak memory 146456 kb
Host smart-a97a20f6-1b76-4973-a40e-c46b5927685e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407059668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3407059668
Directory /workspace/8.prim_esc_test/latest
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