Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.69 95.41 87.80 100.00 92.86 88.89 85.19


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.74 87.74 92.66 92.66 87.80 87.80 100.00 100.00 78.57 78.57 82.22 82.22 85.19 85.19 /workspace/coverage/default/11.prim_esc_test.17140833
89.45 1.71 93.58 0.92 87.80 0.00 100.00 0.00 85.71 7.14 84.44 2.22 85.19 0.00 /workspace/coverage/default/0.prim_esc_test.603078049
90.57 1.12 94.50 0.92 87.80 0.00 100.00 0.00 89.29 3.57 86.67 2.22 85.19 0.00 /workspace/coverage/default/13.prim_esc_test.3658834699
91.69 1.12 95.41 0.92 87.80 0.00 100.00 0.00 92.86 3.57 88.89 2.22 85.19 0.00 /workspace/coverage/default/16.prim_esc_test.1060905849

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.4132318898
/workspace/coverage/default/10.prim_esc_test.3063547928
/workspace/coverage/default/12.prim_esc_test.42180071
/workspace/coverage/default/14.prim_esc_test.120135722
/workspace/coverage/default/15.prim_esc_test.3406401674
/workspace/coverage/default/17.prim_esc_test.2123686722
/workspace/coverage/default/18.prim_esc_test.3073655172
/workspace/coverage/default/19.prim_esc_test.1041374884
/workspace/coverage/default/2.prim_esc_test.2459415076
/workspace/coverage/default/3.prim_esc_test.3101527676
/workspace/coverage/default/4.prim_esc_test.180158714
/workspace/coverage/default/5.prim_esc_test.3062584987
/workspace/coverage/default/6.prim_esc_test.1283229586
/workspace/coverage/default/7.prim_esc_test.920030304
/workspace/coverage/default/8.prim_esc_test.136779935
/workspace/coverage/default/9.prim_esc_test.2977381804



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/15.prim_esc_test.3406401674 Aug 11 04:36:20 PM PDT 24 Aug 11 04:36:20 PM PDT 24 4809791 ps
T2 /workspace/coverage/default/9.prim_esc_test.2977381804 Aug 11 04:37:09 PM PDT 24 Aug 11 04:37:10 PM PDT 24 4831929 ps
T3 /workspace/coverage/default/14.prim_esc_test.120135722 Aug 11 04:36:07 PM PDT 24 Aug 11 04:36:08 PM PDT 24 4981992 ps
T8 /workspace/coverage/default/13.prim_esc_test.3658834699 Aug 11 04:36:33 PM PDT 24 Aug 11 04:36:33 PM PDT 24 4583084 ps
T4 /workspace/coverage/default/0.prim_esc_test.603078049 Aug 11 04:36:16 PM PDT 24 Aug 11 04:36:17 PM PDT 24 5083075 ps
T7 /workspace/coverage/default/3.prim_esc_test.3101527676 Aug 11 04:37:09 PM PDT 24 Aug 11 04:37:10 PM PDT 24 5014740 ps
T13 /workspace/coverage/default/6.prim_esc_test.1283229586 Aug 11 04:36:25 PM PDT 24 Aug 11 04:36:26 PM PDT 24 4486410 ps
T5 /workspace/coverage/default/1.prim_esc_test.4132318898 Aug 11 04:35:59 PM PDT 24 Aug 11 04:36:00 PM PDT 24 5136488 ps
T6 /workspace/coverage/default/11.prim_esc_test.17140833 Aug 11 04:36:19 PM PDT 24 Aug 11 04:36:19 PM PDT 24 4963336 ps
T12 /workspace/coverage/default/8.prim_esc_test.136779935 Aug 11 04:36:13 PM PDT 24 Aug 11 04:36:14 PM PDT 24 4816305 ps
T9 /workspace/coverage/default/5.prim_esc_test.3062584987 Aug 11 04:36:13 PM PDT 24 Aug 11 04:36:13 PM PDT 24 4554147 ps
T11 /workspace/coverage/default/16.prim_esc_test.1060905849 Aug 11 04:36:10 PM PDT 24 Aug 11 04:36:10 PM PDT 24 4763295 ps
T14 /workspace/coverage/default/18.prim_esc_test.3073655172 Aug 11 04:36:30 PM PDT 24 Aug 11 04:36:31 PM PDT 24 4395262 ps
T15 /workspace/coverage/default/19.prim_esc_test.1041374884 Aug 11 04:36:10 PM PDT 24 Aug 11 04:36:10 PM PDT 24 5061046 ps
T16 /workspace/coverage/default/7.prim_esc_test.920030304 Aug 11 04:36:07 PM PDT 24 Aug 11 04:36:07 PM PDT 24 5045839 ps
T10 /workspace/coverage/default/17.prim_esc_test.2123686722 Aug 11 04:36:32 PM PDT 24 Aug 11 04:36:32 PM PDT 24 5283399 ps
T17 /workspace/coverage/default/4.prim_esc_test.180158714 Aug 11 04:36:12 PM PDT 24 Aug 11 04:36:13 PM PDT 24 4840929 ps
T18 /workspace/coverage/default/2.prim_esc_test.2459415076 Aug 11 04:36:25 PM PDT 24 Aug 11 04:36:25 PM PDT 24 4671274 ps
T19 /workspace/coverage/default/12.prim_esc_test.42180071 Aug 11 04:36:23 PM PDT 24 Aug 11 04:36:23 PM PDT 24 5062142 ps
T20 /workspace/coverage/default/10.prim_esc_test.3063547928 Aug 11 04:37:09 PM PDT 24 Aug 11 04:37:10 PM PDT 24 5375192 ps

Test location /workspace/coverage/default/11.prim_esc_test.17140833
Short name T6
Test name
Test status
Simulation time 4963336 ps
CPU time 0.39 seconds
Started Aug 11 04:36:19 PM PDT 24
Finished Aug 11 04:36:19 PM PDT 24
Peak memory 146476 kb
Host smart-2c0f9dea-e884-4c2f-85db-68708e6e13e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17140833 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.17140833
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.603078049
Short name T4
Test name
Test status
Simulation time 5083075 ps
CPU time 0.39 seconds
Started Aug 11 04:36:16 PM PDT 24
Finished Aug 11 04:36:17 PM PDT 24
Peak memory 146384 kb
Host smart-66d06a83-c231-40dc-845c-78eb6062e089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603078049 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.603078049
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.3658834699
Short name T8
Test name
Test status
Simulation time 4583084 ps
CPU time 0.37 seconds
Started Aug 11 04:36:33 PM PDT 24
Finished Aug 11 04:36:33 PM PDT 24
Peak memory 146404 kb
Host smart-40cb932c-4d53-43d1-bc04-cda089c4352a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658834699 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.3658834699
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.1060905849
Short name T11
Test name
Test status
Simulation time 4763295 ps
CPU time 0.37 seconds
Started Aug 11 04:36:10 PM PDT 24
Finished Aug 11 04:36:10 PM PDT 24
Peak memory 146372 kb
Host smart-f5b089c6-03e6-42c8-8c71-34c53ce6bb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060905849 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1060905849
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.4132318898
Short name T5
Test name
Test status
Simulation time 5136488 ps
CPU time 0.37 seconds
Started Aug 11 04:35:59 PM PDT 24
Finished Aug 11 04:36:00 PM PDT 24
Peak memory 146408 kb
Host smart-4a26197b-066a-4ed4-9ba2-c1ca5ca8df00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132318898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.4132318898
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.3063547928
Short name T20
Test name
Test status
Simulation time 5375192 ps
CPU time 0.43 seconds
Started Aug 11 04:37:09 PM PDT 24
Finished Aug 11 04:37:10 PM PDT 24
Peak memory 144288 kb
Host smart-74192d93-9207-4c63-a415-cf2b2f0eb00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063547928 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3063547928
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.42180071
Short name T19
Test name
Test status
Simulation time 5062142 ps
CPU time 0.42 seconds
Started Aug 11 04:36:23 PM PDT 24
Finished Aug 11 04:36:23 PM PDT 24
Peak memory 146472 kb
Host smart-e105abb9-1ae3-4be4-b9b8-c8962f93cf88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42180071 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.42180071
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.120135722
Short name T3
Test name
Test status
Simulation time 4981992 ps
CPU time 0.37 seconds
Started Aug 11 04:36:07 PM PDT 24
Finished Aug 11 04:36:08 PM PDT 24
Peak memory 146432 kb
Host smart-42f55ddc-510c-4ae7-9be4-6843d0c0138f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120135722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.120135722
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.3406401674
Short name T1
Test name
Test status
Simulation time 4809791 ps
CPU time 0.42 seconds
Started Aug 11 04:36:20 PM PDT 24
Finished Aug 11 04:36:20 PM PDT 24
Peak memory 146388 kb
Host smart-59eb0175-e3c2-4dfc-a8ec-5fb7125e08af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406401674 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3406401674
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.2123686722
Short name T10
Test name
Test status
Simulation time 5283399 ps
CPU time 0.39 seconds
Started Aug 11 04:36:32 PM PDT 24
Finished Aug 11 04:36:32 PM PDT 24
Peak memory 146404 kb
Host smart-a0f377e0-b50f-404b-9050-52687f6184e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123686722 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2123686722
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.3073655172
Short name T14
Test name
Test status
Simulation time 4395262 ps
CPU time 0.38 seconds
Started Aug 11 04:36:30 PM PDT 24
Finished Aug 11 04:36:31 PM PDT 24
Peak memory 146400 kb
Host smart-c9be9280-d916-4c11-8bdf-edbf185e16f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073655172 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3073655172
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.1041374884
Short name T15
Test name
Test status
Simulation time 5061046 ps
CPU time 0.37 seconds
Started Aug 11 04:36:10 PM PDT 24
Finished Aug 11 04:36:10 PM PDT 24
Peak memory 146372 kb
Host smart-e779c6a9-9f5c-4af6-b00d-ed7f2adf2137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041374884 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1041374884
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.2459415076
Short name T18
Test name
Test status
Simulation time 4671274 ps
CPU time 0.38 seconds
Started Aug 11 04:36:25 PM PDT 24
Finished Aug 11 04:36:25 PM PDT 24
Peak memory 146352 kb
Host smart-76da648e-c456-4a5f-b009-ee97d076ccc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459415076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2459415076
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.3101527676
Short name T7
Test name
Test status
Simulation time 5014740 ps
CPU time 0.45 seconds
Started Aug 11 04:37:09 PM PDT 24
Finished Aug 11 04:37:10 PM PDT 24
Peak memory 145352 kb
Host smart-a18308fe-a697-469a-a4be-95eb39d49b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101527676 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3101527676
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.180158714
Short name T17
Test name
Test status
Simulation time 4840929 ps
CPU time 0.39 seconds
Started Aug 11 04:36:12 PM PDT 24
Finished Aug 11 04:36:13 PM PDT 24
Peak memory 146396 kb
Host smart-08f44892-9391-4ea5-b409-f90ebadbd8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180158714 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.180158714
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.3062584987
Short name T9
Test name
Test status
Simulation time 4554147 ps
CPU time 0.39 seconds
Started Aug 11 04:36:13 PM PDT 24
Finished Aug 11 04:36:13 PM PDT 24
Peak memory 147168 kb
Host smart-d71dc5f5-9492-4183-b023-a621dd8ef53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062584987 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3062584987
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.1283229586
Short name T13
Test name
Test status
Simulation time 4486410 ps
CPU time 0.42 seconds
Started Aug 11 04:36:25 PM PDT 24
Finished Aug 11 04:36:26 PM PDT 24
Peak memory 146384 kb
Host smart-1fecf964-3aa3-485f-88be-b6ba184ab807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283229586 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1283229586
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.920030304
Short name T16
Test name
Test status
Simulation time 5045839 ps
CPU time 0.38 seconds
Started Aug 11 04:36:07 PM PDT 24
Finished Aug 11 04:36:07 PM PDT 24
Peak memory 146420 kb
Host smart-76fe4c60-306e-4c88-9da0-32883eb439f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920030304 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.920030304
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.136779935
Short name T12
Test name
Test status
Simulation time 4816305 ps
CPU time 0.39 seconds
Started Aug 11 04:36:13 PM PDT 24
Finished Aug 11 04:36:14 PM PDT 24
Peak memory 146448 kb
Host smart-26574a9d-75c4-4f31-b82a-213d103e5a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136779935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.136779935
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.2977381804
Short name T2
Test name
Test status
Simulation time 4831929 ps
CPU time 0.36 seconds
Started Aug 11 04:37:09 PM PDT 24
Finished Aug 11 04:37:10 PM PDT 24
Peak memory 146792 kb
Host smart-3f678da2-acb8-4df3-8722-af3a280888dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977381804 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2977381804
Directory /workspace/9.prim_esc_test/latest
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