| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.74 | 86.74 | 92.66 | 92.66 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/16.prim_esc_test.1623875852 |
| 89.45 | 2.72 | 93.58 | 0.92 | 87.80 | 2.44 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/11.prim_esc_test.3767841600 |
| 91.17 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/5.prim_esc_test.2810431376 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/17.prim_esc_test.1867867047 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1822463207 |
| /workspace/coverage/default/1.prim_esc_test.3055123147 |
| /workspace/coverage/default/10.prim_esc_test.769155745 |
| /workspace/coverage/default/12.prim_esc_test.3570817146 |
| /workspace/coverage/default/13.prim_esc_test.1941980876 |
| /workspace/coverage/default/14.prim_esc_test.2380995102 |
| /workspace/coverage/default/15.prim_esc_test.1182522765 |
| /workspace/coverage/default/18.prim_esc_test.1603312874 |
| /workspace/coverage/default/19.prim_esc_test.2662471285 |
| /workspace/coverage/default/2.prim_esc_test.1292594132 |
| /workspace/coverage/default/3.prim_esc_test.3078798546 |
| /workspace/coverage/default/4.prim_esc_test.3255765272 |
| /workspace/coverage/default/6.prim_esc_test.4200955096 |
| /workspace/coverage/default/7.prim_esc_test.3672419198 |
| /workspace/coverage/default/8.prim_esc_test.3459590960 |
| /workspace/coverage/default/9.prim_esc_test.1247709469 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/2.prim_esc_test.1292594132 | Aug 12 05:28:43 PM PDT 24 | Aug 12 05:28:48 PM PDT 24 | 5114937 ps | ||
| T2 | /workspace/coverage/default/10.prim_esc_test.769155745 | Aug 12 05:29:05 PM PDT 24 | Aug 12 05:29:05 PM PDT 24 | 5109643 ps | ||
| T3 | /workspace/coverage/default/3.prim_esc_test.3078798546 | Aug 12 05:28:49 PM PDT 24 | Aug 12 05:28:50 PM PDT 24 | 5313064 ps | ||
| T4 | /workspace/coverage/default/8.prim_esc_test.3459590960 | Aug 12 05:28:41 PM PDT 24 | Aug 12 05:28:41 PM PDT 24 | 4949615 ps | ||
| T5 | /workspace/coverage/default/14.prim_esc_test.2380995102 | Aug 12 05:28:39 PM PDT 24 | Aug 12 05:28:39 PM PDT 24 | 5374724 ps | ||
| T6 | /workspace/coverage/default/13.prim_esc_test.1941980876 | Aug 12 05:29:10 PM PDT 24 | Aug 12 05:29:16 PM PDT 24 | 4748419 ps | ||
| T14 | /workspace/coverage/default/19.prim_esc_test.2662471285 | Aug 12 05:28:49 PM PDT 24 | Aug 12 05:28:49 PM PDT 24 | 5121549 ps | ||
| T7 | /workspace/coverage/default/16.prim_esc_test.1623875852 | Aug 12 05:28:50 PM PDT 24 | Aug 12 05:28:50 PM PDT 24 | 4961352 ps | ||
| T8 | /workspace/coverage/default/9.prim_esc_test.1247709469 | Aug 12 05:28:48 PM PDT 24 | Aug 12 05:28:48 PM PDT 24 | 4816799 ps | ||
| T15 | /workspace/coverage/default/12.prim_esc_test.3570817146 | Aug 12 05:28:44 PM PDT 24 | Aug 12 05:28:45 PM PDT 24 | 4846108 ps | ||
| T11 | /workspace/coverage/default/17.prim_esc_test.1867867047 | Aug 12 05:28:42 PM PDT 24 | Aug 12 05:28:42 PM PDT 24 | 4405400 ps | ||
| T12 | /workspace/coverage/default/7.prim_esc_test.3672419198 | Aug 12 05:28:54 PM PDT 24 | Aug 12 05:28:54 PM PDT 24 | 4885447 ps | ||
| T16 | /workspace/coverage/default/6.prim_esc_test.4200955096 | Aug 12 05:28:48 PM PDT 24 | Aug 12 05:28:49 PM PDT 24 | 5016014 ps | ||
| T13 | /workspace/coverage/default/0.prim_esc_test.1822463207 | Aug 12 05:28:46 PM PDT 24 | Aug 12 05:28:47 PM PDT 24 | 4366848 ps | ||
| T9 | /workspace/coverage/default/5.prim_esc_test.2810431376 | Aug 12 05:28:39 PM PDT 24 | Aug 12 05:28:40 PM PDT 24 | 4748906 ps | ||
| T18 | /workspace/coverage/default/18.prim_esc_test.1603312874 | Aug 12 05:28:58 PM PDT 24 | Aug 12 05:28:58 PM PDT 24 | 4698304 ps | ||
| T19 | /workspace/coverage/default/1.prim_esc_test.3055123147 | Aug 12 05:28:55 PM PDT 24 | Aug 12 05:28:56 PM PDT 24 | 4374805 ps | ||
| T20 | /workspace/coverage/default/4.prim_esc_test.3255765272 | Aug 12 05:28:40 PM PDT 24 | Aug 12 05:28:40 PM PDT 24 | 4754950 ps | ||
| T17 | /workspace/coverage/default/11.prim_esc_test.3767841600 | Aug 12 05:28:49 PM PDT 24 | Aug 12 05:28:50 PM PDT 24 | 4274102 ps | ||
| T10 | /workspace/coverage/default/15.prim_esc_test.1182522765 | Aug 12 05:28:55 PM PDT 24 | Aug 12 05:28:56 PM PDT 24 | 4545299 ps |
| Test location | /workspace/coverage/default/16.prim_esc_test.1623875852 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4961352 ps |
| CPU time | 0.39 seconds |
| Started | Aug 12 05:28:50 PM PDT 24 |
| Finished | Aug 12 05:28:50 PM PDT 24 |
| Peak memory | 146544 kb |
| Host | smart-4beec067-4841-4b53-ad39-2da4b7c55aca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1623875852 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1623875852 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.3767841600 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4274102 ps |
| CPU time | 0.37 seconds |
| Started | Aug 12 05:28:49 PM PDT 24 |
| Finished | Aug 12 05:28:50 PM PDT 24 |
| Peak memory | 146460 kb |
| Host | smart-6d9b0441-bc61-4d28-8bc5-283c812a4909 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3767841600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3767841600 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2810431376 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4748906 ps |
| CPU time | 0.4 seconds |
| Started | Aug 12 05:28:39 PM PDT 24 |
| Finished | Aug 12 05:28:40 PM PDT 24 |
| Peak memory | 146532 kb |
| Host | smart-808ba4c4-cdf5-416d-a1a3-b3774e173c12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2810431376 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2810431376 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1867867047 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4405400 ps |
| CPU time | 0.36 seconds |
| Started | Aug 12 05:28:42 PM PDT 24 |
| Finished | Aug 12 05:28:42 PM PDT 24 |
| Peak memory | 146532 kb |
| Host | smart-42a97aa9-8169-4cd9-941e-822cb63db207 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867867047 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1867867047 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1822463207 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4366848 ps |
| CPU time | 0.38 seconds |
| Started | Aug 12 05:28:46 PM PDT 24 |
| Finished | Aug 12 05:28:47 PM PDT 24 |
| Peak memory | 146628 kb |
| Host | smart-39a2da26-7ee6-48d4-a6c1-2121b5de0155 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1822463207 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1822463207 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3055123147 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4374805 ps |
| CPU time | 0.37 seconds |
| Started | Aug 12 05:28:55 PM PDT 24 |
| Finished | Aug 12 05:28:56 PM PDT 24 |
| Peak memory | 146440 kb |
| Host | smart-1b545a87-3434-40a8-bc6b-c0cc8d291594 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3055123147 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3055123147 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.769155745 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5109643 ps |
| CPU time | 0.41 seconds |
| Started | Aug 12 05:29:05 PM PDT 24 |
| Finished | Aug 12 05:29:05 PM PDT 24 |
| Peak memory | 146536 kb |
| Host | smart-bcb98b73-5460-4e00-ae1f-33a525105609 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=769155745 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.769155745 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3570817146 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4846108 ps |
| CPU time | 0.4 seconds |
| Started | Aug 12 05:28:44 PM PDT 24 |
| Finished | Aug 12 05:28:45 PM PDT 24 |
| Peak memory | 146528 kb |
| Host | smart-e120c1d4-ef57-4102-b492-a8b5bac88897 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570817146 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3570817146 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.1941980876 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4748419 ps |
| CPU time | 0.39 seconds |
| Started | Aug 12 05:29:10 PM PDT 24 |
| Finished | Aug 12 05:29:16 PM PDT 24 |
| Peak memory | 146528 kb |
| Host | smart-f5489bd5-195f-4070-b595-d17d86771cb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1941980876 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.1941980876 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2380995102 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5374724 ps |
| CPU time | 0.38 seconds |
| Started | Aug 12 05:28:39 PM PDT 24 |
| Finished | Aug 12 05:28:39 PM PDT 24 |
| Peak memory | 146528 kb |
| Host | smart-6d20841b-ce4c-4434-aacd-80533d9d7b4b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380995102 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2380995102 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1182522765 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4545299 ps |
| CPU time | 0.36 seconds |
| Started | Aug 12 05:28:55 PM PDT 24 |
| Finished | Aug 12 05:28:56 PM PDT 24 |
| Peak memory | 146592 kb |
| Host | smart-135927c1-dda0-44fc-a36d-d5085af924fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1182522765 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1182522765 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.1603312874 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4698304 ps |
| CPU time | 0.37 seconds |
| Started | Aug 12 05:28:58 PM PDT 24 |
| Finished | Aug 12 05:28:58 PM PDT 24 |
| Peak memory | 146544 kb |
| Host | smart-1dc6e4e7-f0a1-4f8b-a755-40e0fd20c866 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1603312874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1603312874 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2662471285 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5121549 ps |
| CPU time | 0.39 seconds |
| Started | Aug 12 05:28:49 PM PDT 24 |
| Finished | Aug 12 05:28:49 PM PDT 24 |
| Peak memory | 146552 kb |
| Host | smart-fca9454a-6b88-46e2-8a56-d3d105a961ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2662471285 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2662471285 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1292594132 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5114937 ps |
| CPU time | 0.39 seconds |
| Started | Aug 12 05:28:43 PM PDT 24 |
| Finished | Aug 12 05:28:48 PM PDT 24 |
| Peak memory | 146444 kb |
| Host | smart-e0cf47ea-998a-4b44-9e82-45e0edb50689 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1292594132 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1292594132 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.3078798546 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5313064 ps |
| CPU time | 0.37 seconds |
| Started | Aug 12 05:28:49 PM PDT 24 |
| Finished | Aug 12 05:28:50 PM PDT 24 |
| Peak memory | 146476 kb |
| Host | smart-cf6e213f-b293-4882-93a1-0f1e811b6f32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3078798546 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3078798546 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.3255765272 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4754950 ps |
| CPU time | 0.36 seconds |
| Started | Aug 12 05:28:40 PM PDT 24 |
| Finished | Aug 12 05:28:40 PM PDT 24 |
| Peak memory | 146528 kb |
| Host | smart-09bc9066-2698-44bb-ab7e-9425bf37fe55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3255765272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3255765272 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.4200955096 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5016014 ps |
| CPU time | 0.39 seconds |
| Started | Aug 12 05:28:48 PM PDT 24 |
| Finished | Aug 12 05:28:49 PM PDT 24 |
| Peak memory | 146536 kb |
| Host | smart-ed6f65ce-20dc-4b35-ae86-6c6addc8f13e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4200955096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4200955096 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3672419198 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4885447 ps |
| CPU time | 0.39 seconds |
| Started | Aug 12 05:28:54 PM PDT 24 |
| Finished | Aug 12 05:28:54 PM PDT 24 |
| Peak memory | 146508 kb |
| Host | smart-0574b043-f768-4adc-9303-3f0e837631fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3672419198 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3672419198 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3459590960 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4949615 ps |
| CPU time | 0.37 seconds |
| Started | Aug 12 05:28:41 PM PDT 24 |
| Finished | Aug 12 05:28:41 PM PDT 24 |
| Peak memory | 146516 kb |
| Host | smart-e640adde-76d7-4e23-929f-d39079e9c06a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3459590960 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3459590960 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.1247709469 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4816799 ps |
| CPU time | 0.38 seconds |
| Started | Aug 12 05:28:48 PM PDT 24 |
| Finished | Aug 12 05:28:48 PM PDT 24 |
| Peak memory | 146628 kb |
| Host | smart-2db95d7c-dfdb-40a5-868c-2989a9f18e7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1247709469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.1247709469 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |