| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/18.prim_esc_test.3521965595 |
| 88.86 | 1.71 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/4.prim_esc_test.1798274599 |
| 90.57 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/9.prim_esc_test.3810522339 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/14.prim_esc_test.2522131165 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspace/coverage/default/1.prim_esc_test.2415924982 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.245273411 |
| /workspace/coverage/default/10.prim_esc_test.3155511675 |
| /workspace/coverage/default/11.prim_esc_test.2196000230 |
| /workspace/coverage/default/12.prim_esc_test.4242815936 |
| /workspace/coverage/default/13.prim_esc_test.560465054 |
| /workspace/coverage/default/15.prim_esc_test.4290064838 |
| /workspace/coverage/default/16.prim_esc_test.1063289043 |
| /workspace/coverage/default/17.prim_esc_test.1049589091 |
| /workspace/coverage/default/19.prim_esc_test.2020820721 |
| /workspace/coverage/default/2.prim_esc_test.2036005024 |
| /workspace/coverage/default/3.prim_esc_test.4193707296 |
| /workspace/coverage/default/5.prim_esc_test.402341344 |
| /workspace/coverage/default/6.prim_esc_test.2260174065 |
| /workspace/coverage/default/7.prim_esc_test.3376768571 |
| /workspace/coverage/default/8.prim_esc_test.1430687364 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/3.prim_esc_test.4193707296 | Aug 13 04:46:06 PM PDT 24 | Aug 13 04:46:06 PM PDT 24 | 4698585 ps | ||
| T2 | /workspace/coverage/default/14.prim_esc_test.2522131165 | Aug 13 04:46:10 PM PDT 24 | Aug 13 04:46:11 PM PDT 24 | 4611228 ps | ||
| T3 | /workspace/coverage/default/9.prim_esc_test.3810522339 | Aug 13 04:46:03 PM PDT 24 | Aug 13 04:46:04 PM PDT 24 | 5173310 ps | ||
| T6 | /workspace/coverage/default/5.prim_esc_test.402341344 | Aug 13 04:46:03 PM PDT 24 | Aug 13 04:46:03 PM PDT 24 | 4516695 ps | ||
| T7 | /workspace/coverage/default/8.prim_esc_test.1430687364 | Aug 13 04:46:05 PM PDT 24 | Aug 13 04:46:05 PM PDT 24 | 4959733 ps | ||
| T14 | /workspace/coverage/default/7.prim_esc_test.3376768571 | Aug 13 04:46:02 PM PDT 24 | Aug 13 04:46:02 PM PDT 24 | 4392575 ps | ||
| T10 | /workspace/coverage/default/13.prim_esc_test.560465054 | Aug 13 04:46:11 PM PDT 24 | Aug 13 04:46:11 PM PDT 24 | 5121481 ps | ||
| T15 | /workspace/coverage/default/10.prim_esc_test.3155511675 | Aug 13 04:46:05 PM PDT 24 | Aug 13 04:46:06 PM PDT 24 | 4674064 ps | ||
| T4 | /workspace/coverage/default/16.prim_esc_test.1063289043 | Aug 13 04:46:09 PM PDT 24 | Aug 13 04:46:10 PM PDT 24 | 4753817 ps | ||
| T5 | /workspace/coverage/default/18.prim_esc_test.3521965595 | Aug 13 04:46:12 PM PDT 24 | Aug 13 04:46:12 PM PDT 24 | 5038295 ps | ||
| T16 | /workspace/coverage/default/15.prim_esc_test.4290064838 | Aug 13 04:46:10 PM PDT 24 | Aug 13 04:46:10 PM PDT 24 | 4905316 ps | ||
| T8 | /workspace/coverage/default/4.prim_esc_test.1798274599 | Aug 13 04:46:03 PM PDT 24 | Aug 13 04:46:03 PM PDT 24 | 4782371 ps | ||
| T17 | /workspace/coverage/default/12.prim_esc_test.4242815936 | Aug 13 04:46:02 PM PDT 24 | Aug 13 04:46:03 PM PDT 24 | 5423603 ps | ||
| T9 | /workspace/coverage/default/2.prim_esc_test.2036005024 | Aug 13 04:46:02 PM PDT 24 | Aug 13 04:46:02 PM PDT 24 | 5076298 ps | ||
| T18 | /workspace/coverage/default/19.prim_esc_test.2020820721 | Aug 13 04:46:09 PM PDT 24 | Aug 13 04:46:10 PM PDT 24 | 5450603 ps | ||
| T12 | /workspace/coverage/default/17.prim_esc_test.1049589091 | Aug 13 04:46:09 PM PDT 24 | Aug 13 04:46:10 PM PDT 24 | 4920167 ps | ||
| T13 | /workspace/coverage/default/1.prim_esc_test.2415924982 | Aug 13 04:46:00 PM PDT 24 | Aug 13 04:46:01 PM PDT 24 | 4965370 ps | ||
| T11 | /workspace/coverage/default/6.prim_esc_test.2260174065 | Aug 13 04:46:05 PM PDT 24 | Aug 13 04:46:06 PM PDT 24 | 4507562 ps | ||
| T19 | /workspace/coverage/default/0.prim_esc_test.245273411 | Aug 13 04:46:03 PM PDT 24 | Aug 13 04:46:03 PM PDT 24 | 4602661 ps | ||
| T20 | /workspace/coverage/default/11.prim_esc_test.2196000230 | Aug 13 04:46:03 PM PDT 24 | Aug 13 04:46:04 PM PDT 24 | 4393795 ps |
| Test location | /workspace/coverage/default/18.prim_esc_test.3521965595 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5038295 ps |
| CPU time | 0.39 seconds |
| Started | Aug 13 04:46:12 PM PDT 24 |
| Finished | Aug 13 04:46:12 PM PDT 24 |
| Peak memory | 146520 kb |
| Host | smart-3d79832c-b47b-4ba2-b9d2-071be03b1376 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3521965595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3521965595 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1798274599 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4782371 ps |
| CPU time | 0.39 seconds |
| Started | Aug 13 04:46:03 PM PDT 24 |
| Finished | Aug 13 04:46:03 PM PDT 24 |
| Peak memory | 146492 kb |
| Host | smart-fe7e4be2-3338-42bf-9af0-83d9c3f80357 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798274599 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1798274599 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3810522339 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5173310 ps |
| CPU time | 0.39 seconds |
| Started | Aug 13 04:46:03 PM PDT 24 |
| Finished | Aug 13 04:46:04 PM PDT 24 |
| Peak memory | 146412 kb |
| Host | smart-c99b1339-31c3-4390-9c84-92f637b10af0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3810522339 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3810522339 |
| Directory | /workspace/9.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2522131165 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4611228 ps |
| CPU time | 0.41 seconds |
| Started | Aug 13 04:46:10 PM PDT 24 |
| Finished | Aug 13 04:46:11 PM PDT 24 |
| Peak memory | 146400 kb |
| Host | smart-4b8536cf-f13f-47ce-83b1-f16a5a9235a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2522131165 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2522131165 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.2415924982 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4965370 ps |
| CPU time | 0.39 seconds |
| Started | Aug 13 04:46:00 PM PDT 24 |
| Finished | Aug 13 04:46:01 PM PDT 24 |
| Peak memory | 146432 kb |
| Host | smart-4ce7c1ca-0ac9-4f62-a8ce-d94824c8b4d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2415924982 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2415924982 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.245273411 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4602661 ps |
| CPU time | 0.39 seconds |
| Started | Aug 13 04:46:03 PM PDT 24 |
| Finished | Aug 13 04:46:03 PM PDT 24 |
| Peak memory | 146396 kb |
| Host | smart-49b4ff7d-1f15-407e-9080-9fa199551ba6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=245273411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.245273411 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.3155511675 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4674064 ps |
| CPU time | 0.38 seconds |
| Started | Aug 13 04:46:05 PM PDT 24 |
| Finished | Aug 13 04:46:06 PM PDT 24 |
| Peak memory | 146412 kb |
| Host | smart-3cea2aa6-8db3-4a8b-b4a8-57bc29861637 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3155511675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.3155511675 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2196000230 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4393795 ps |
| CPU time | 0.43 seconds |
| Started | Aug 13 04:46:03 PM PDT 24 |
| Finished | Aug 13 04:46:04 PM PDT 24 |
| Peak memory | 146404 kb |
| Host | smart-954f35ff-c408-4029-8881-dd2bf62fb0a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2196000230 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2196000230 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.4242815936 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5423603 ps |
| CPU time | 0.4 seconds |
| Started | Aug 13 04:46:02 PM PDT 24 |
| Finished | Aug 13 04:46:03 PM PDT 24 |
| Peak memory | 146416 kb |
| Host | smart-ca1eb63b-0f14-4b93-a4e6-cdea4bcc6425 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4242815936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.4242815936 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.560465054 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5121481 ps |
| CPU time | 0.38 seconds |
| Started | Aug 13 04:46:11 PM PDT 24 |
| Finished | Aug 13 04:46:11 PM PDT 24 |
| Peak memory | 146468 kb |
| Host | smart-f211f4a2-5eba-4dd0-8c17-f7ba9ac95f51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560465054 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.560465054 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.4290064838 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4905316 ps |
| CPU time | 0.39 seconds |
| Started | Aug 13 04:46:10 PM PDT 24 |
| Finished | Aug 13 04:46:10 PM PDT 24 |
| Peak memory | 146488 kb |
| Host | smart-6f9dbd07-6daf-47f4-986f-8dd309d4a75d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4290064838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.4290064838 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1063289043 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4753817 ps |
| CPU time | 0.38 seconds |
| Started | Aug 13 04:46:09 PM PDT 24 |
| Finished | Aug 13 04:46:10 PM PDT 24 |
| Peak memory | 146524 kb |
| Host | smart-541dd485-fadc-44e5-8580-fb7e1beff572 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063289043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1063289043 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1049589091 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4920167 ps |
| CPU time | 0.38 seconds |
| Started | Aug 13 04:46:09 PM PDT 24 |
| Finished | Aug 13 04:46:10 PM PDT 24 |
| Peak memory | 146412 kb |
| Host | smart-1f81ff88-199a-45af-9f22-50af79d85478 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1049589091 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1049589091 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2020820721 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5450603 ps |
| CPU time | 0.38 seconds |
| Started | Aug 13 04:46:09 PM PDT 24 |
| Finished | Aug 13 04:46:10 PM PDT 24 |
| Peak memory | 146412 kb |
| Host | smart-cfa5d38d-2b0b-4696-88cd-c55d819520f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2020820721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2020820721 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.2036005024 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5076298 ps |
| CPU time | 0.38 seconds |
| Started | Aug 13 04:46:02 PM PDT 24 |
| Finished | Aug 13 04:46:02 PM PDT 24 |
| Peak memory | 146432 kb |
| Host | smart-b5a7a55b-3c85-4157-a6eb-99b5fed2ac9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2036005024 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2036005024 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.4193707296 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4698585 ps |
| CPU time | 0.38 seconds |
| Started | Aug 13 04:46:06 PM PDT 24 |
| Finished | Aug 13 04:46:06 PM PDT 24 |
| Peak memory | 146412 kb |
| Host | smart-2754c3f7-0812-4948-916c-4ed501ad31c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4193707296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.4193707296 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.402341344 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4516695 ps |
| CPU time | 0.41 seconds |
| Started | Aug 13 04:46:03 PM PDT 24 |
| Finished | Aug 13 04:46:03 PM PDT 24 |
| Peak memory | 146432 kb |
| Host | smart-1950141e-9627-4ffa-a925-97a24fad41fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402341344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.402341344 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2260174065 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4507562 ps |
| CPU time | 0.38 seconds |
| Started | Aug 13 04:46:05 PM PDT 24 |
| Finished | Aug 13 04:46:06 PM PDT 24 |
| Peak memory | 146412 kb |
| Host | smart-58f46a7f-fd09-4907-9257-6f03f7d304b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2260174065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2260174065 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3376768571 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4392575 ps |
| CPU time | 0.39 seconds |
| Started | Aug 13 04:46:02 PM PDT 24 |
| Finished | Aug 13 04:46:02 PM PDT 24 |
| Peak memory | 146424 kb |
| Host | smart-54b3da63-9601-40cf-9d32-c5e24392bb2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376768571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3376768571 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1430687364 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4959733 ps |
| CPU time | 0.38 seconds |
| Started | Aug 13 04:46:05 PM PDT 24 |
| Finished | Aug 13 04:46:05 PM PDT 24 |
| Peak memory | 146376 kb |
| Host | smart-e4334d55-9d73-43be-9998-9f10313592ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1430687364 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1430687364 |
| Directory | /workspace/8.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |