| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/9.prim_esc_test.2637847398 |
| 89.45 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/16.prim_esc_test.2180758951 |
| 91.17 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/1.prim_esc_test.280038723 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/10.prim_esc_test.1067079469 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.3403412770 |
| /workspace/coverage/default/11.prim_esc_test.98978097 |
| /workspace/coverage/default/12.prim_esc_test.1800621747 |
| /workspace/coverage/default/13.prim_esc_test.4042094328 |
| /workspace/coverage/default/14.prim_esc_test.1945267971 |
| /workspace/coverage/default/15.prim_esc_test.3631183461 |
| /workspace/coverage/default/17.prim_esc_test.1716101543 |
| /workspace/coverage/default/18.prim_esc_test.859533756 |
| /workspace/coverage/default/19.prim_esc_test.2685525302 |
| /workspace/coverage/default/2.prim_esc_test.577050763 |
| /workspace/coverage/default/3.prim_esc_test.2261356325 |
| /workspace/coverage/default/4.prim_esc_test.2763048384 |
| /workspace/coverage/default/5.prim_esc_test.2559511446 |
| /workspace/coverage/default/6.prim_esc_test.245214618 |
| /workspace/coverage/default/7.prim_esc_test.3752425154 |
| /workspace/coverage/default/8.prim_esc_test.3206453781 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/8.prim_esc_test.3206453781 | Aug 14 04:25:09 PM PDT 24 | Aug 14 04:25:09 PM PDT 24 | 4913938 ps | ||
| T2 | /workspace/coverage/default/7.prim_esc_test.3752425154 | Aug 14 04:19:29 PM PDT 24 | Aug 14 04:19:29 PM PDT 24 | 5050826 ps | ||
| T3 | /workspace/coverage/default/2.prim_esc_test.577050763 | Aug 14 04:19:32 PM PDT 24 | Aug 14 04:19:33 PM PDT 24 | 4881448 ps | ||
| T5 | /workspace/coverage/default/0.prim_esc_test.3403412770 | Aug 14 04:20:41 PM PDT 24 | Aug 14 04:20:42 PM PDT 24 | 4096515 ps | ||
| T4 | /workspace/coverage/default/18.prim_esc_test.859533756 | Aug 14 04:19:41 PM PDT 24 | Aug 14 04:19:41 PM PDT 24 | 5198522 ps | ||
| T14 | /workspace/coverage/default/13.prim_esc_test.4042094328 | Aug 14 04:19:41 PM PDT 24 | Aug 14 04:19:42 PM PDT 24 | 4647897 ps | ||
| T9 | /workspace/coverage/default/16.prim_esc_test.2180758951 | Aug 14 04:25:07 PM PDT 24 | Aug 14 04:25:07 PM PDT 24 | 4387069 ps | ||
| T6 | /workspace/coverage/default/9.prim_esc_test.2637847398 | Aug 14 04:20:51 PM PDT 24 | Aug 14 04:20:52 PM PDT 24 | 4721784 ps | ||
| T11 | /workspace/coverage/default/12.prim_esc_test.1800621747 | Aug 14 04:19:48 PM PDT 24 | Aug 14 04:19:48 PM PDT 24 | 4685403 ps | ||
| T15 | /workspace/coverage/default/3.prim_esc_test.2261356325 | Aug 14 04:19:35 PM PDT 24 | Aug 14 04:19:36 PM PDT 24 | 5211637 ps | ||
| T7 | /workspace/coverage/default/19.prim_esc_test.2685525302 | Aug 14 04:25:09 PM PDT 24 | Aug 14 04:25:09 PM PDT 24 | 4465548 ps | ||
| T16 | /workspace/coverage/default/5.prim_esc_test.2559511446 | Aug 14 04:19:36 PM PDT 24 | Aug 14 04:19:36 PM PDT 24 | 4613391 ps | ||
| T8 | /workspace/coverage/default/11.prim_esc_test.98978097 | Aug 14 04:19:36 PM PDT 24 | Aug 14 04:19:36 PM PDT 24 | 4939023 ps | ||
| T12 | /workspace/coverage/default/1.prim_esc_test.280038723 | Aug 14 04:20:55 PM PDT 24 | Aug 14 04:20:55 PM PDT 24 | 4933850 ps | ||
| T17 | /workspace/coverage/default/6.prim_esc_test.245214618 | Aug 14 04:19:41 PM PDT 24 | Aug 14 04:19:42 PM PDT 24 | 4948496 ps | ||
| T18 | /workspace/coverage/default/14.prim_esc_test.1945267971 | Aug 14 04:19:43 PM PDT 24 | Aug 14 04:19:43 PM PDT 24 | 4931045 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.1067079469 | Aug 14 04:20:41 PM PDT 24 | Aug 14 04:20:41 PM PDT 24 | 5160479 ps | ||
| T19 | /workspace/coverage/default/15.prim_esc_test.3631183461 | Aug 14 04:25:08 PM PDT 24 | Aug 14 04:25:09 PM PDT 24 | 4984914 ps | ||
| T13 | /workspace/coverage/default/4.prim_esc_test.2763048384 | Aug 14 04:20:54 PM PDT 24 | Aug 14 04:20:55 PM PDT 24 | 5340503 ps | ||
| T20 | /workspace/coverage/default/17.prim_esc_test.1716101543 | Aug 14 04:20:59 PM PDT 24 | Aug 14 04:20:59 PM PDT 24 | 4958606 ps |
| Test location | /workspace/coverage/default/9.prim_esc_test.2637847398 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4721784 ps |
| CPU time | 0.42 seconds |
| Started | Aug 14 04:20:51 PM PDT 24 |
| Finished | Aug 14 04:20:52 PM PDT 24 |
| Peak memory | 146168 kb |
| Host | smart-e41552a7-fdc9-42ea-8f35-ee4ed436b9a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2637847398 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2637847398 |
| Directory | /workspace/9.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.2180758951 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4387069 ps |
| CPU time | 0.39 seconds |
| Started | Aug 14 04:25:07 PM PDT 24 |
| Finished | Aug 14 04:25:07 PM PDT 24 |
| Peak memory | 146696 kb |
| Host | smart-a29364c6-ecac-444e-882e-e949efb5b053 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2180758951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2180758951 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.280038723 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4933850 ps |
| CPU time | 0.38 seconds |
| Started | Aug 14 04:20:55 PM PDT 24 |
| Finished | Aug 14 04:20:55 PM PDT 24 |
| Peak memory | 146128 kb |
| Host | smart-956c01aa-772b-4501-8506-2ee292e2a342 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=280038723 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.280038723 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.1067079469 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5160479 ps |
| CPU time | 0.39 seconds |
| Started | Aug 14 04:20:41 PM PDT 24 |
| Finished | Aug 14 04:20:41 PM PDT 24 |
| Peak memory | 145952 kb |
| Host | smart-5e8ed65c-86d4-40df-8abe-84b139f4801d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1067079469 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1067079469 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.3403412770 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4096515 ps |
| CPU time | 0.39 seconds |
| Started | Aug 14 04:20:41 PM PDT 24 |
| Finished | Aug 14 04:20:42 PM PDT 24 |
| Peak memory | 145864 kb |
| Host | smart-7ad1aecb-6ba5-4ecd-b76e-4854140ab666 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3403412770 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.3403412770 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.98978097 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4939023 ps |
| CPU time | 0.38 seconds |
| Started | Aug 14 04:19:36 PM PDT 24 |
| Finished | Aug 14 04:19:36 PM PDT 24 |
| Peak memory | 146640 kb |
| Host | smart-c27bfa40-bc43-43cc-af49-d6163cab68e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=98978097 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.98978097 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.1800621747 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4685403 ps |
| CPU time | 0.38 seconds |
| Started | Aug 14 04:19:48 PM PDT 24 |
| Finished | Aug 14 04:19:48 PM PDT 24 |
| Peak memory | 146276 kb |
| Host | smart-e102be98-c1a9-469a-ba95-00c6f6f48b12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800621747 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.1800621747 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.4042094328 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4647897 ps |
| CPU time | 0.43 seconds |
| Started | Aug 14 04:19:41 PM PDT 24 |
| Finished | Aug 14 04:19:42 PM PDT 24 |
| Peak memory | 145984 kb |
| Host | smart-c46dd578-77a8-4d74-96dc-b3a5b088119e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4042094328 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4042094328 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1945267971 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4931045 ps |
| CPU time | 0.37 seconds |
| Started | Aug 14 04:19:43 PM PDT 24 |
| Finished | Aug 14 04:19:43 PM PDT 24 |
| Peak memory | 146172 kb |
| Host | smart-56fca92e-fa9b-48ef-99f4-0169e8490ddc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945267971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1945267971 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3631183461 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4984914 ps |
| CPU time | 0.37 seconds |
| Started | Aug 14 04:25:08 PM PDT 24 |
| Finished | Aug 14 04:25:09 PM PDT 24 |
| Peak memory | 146056 kb |
| Host | smart-005d91a4-3520-45e5-936d-10a583025030 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3631183461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3631183461 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1716101543 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4958606 ps |
| CPU time | 0.38 seconds |
| Started | Aug 14 04:20:59 PM PDT 24 |
| Finished | Aug 14 04:20:59 PM PDT 24 |
| Peak memory | 146612 kb |
| Host | smart-06a04a1f-b7e5-4a6f-a994-4381213f3bf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1716101543 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1716101543 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.859533756 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5198522 ps |
| CPU time | 0.41 seconds |
| Started | Aug 14 04:19:41 PM PDT 24 |
| Finished | Aug 14 04:19:41 PM PDT 24 |
| Peak memory | 146112 kb |
| Host | smart-569d1f4a-ac39-4773-972c-b3e476ed18b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=859533756 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.859533756 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2685525302 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4465548 ps |
| CPU time | 0.37 seconds |
| Started | Aug 14 04:25:09 PM PDT 24 |
| Finished | Aug 14 04:25:09 PM PDT 24 |
| Peak memory | 146052 kb |
| Host | smart-b4c8b98e-f740-4641-b6a7-84d51dd309b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685525302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2685525302 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.577050763 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4881448 ps |
| CPU time | 0.42 seconds |
| Started | Aug 14 04:19:32 PM PDT 24 |
| Finished | Aug 14 04:19:33 PM PDT 24 |
| Peak memory | 147176 kb |
| Host | smart-214422a7-f612-4be6-8c4a-10c1023a10f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=577050763 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.577050763 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.2261356325 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5211637 ps |
| CPU time | 0.37 seconds |
| Started | Aug 14 04:19:35 PM PDT 24 |
| Finished | Aug 14 04:19:36 PM PDT 24 |
| Peak memory | 146600 kb |
| Host | smart-4022666d-bdb3-4ca7-91c3-9e15daedf4f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2261356325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2261356325 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2763048384 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5340503 ps |
| CPU time | 0.38 seconds |
| Started | Aug 14 04:20:54 PM PDT 24 |
| Finished | Aug 14 04:20:55 PM PDT 24 |
| Peak memory | 146128 kb |
| Host | smart-4805a597-5553-443c-bd1c-01327cd49743 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2763048384 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2763048384 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.2559511446 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4613391 ps |
| CPU time | 0.39 seconds |
| Started | Aug 14 04:19:36 PM PDT 24 |
| Finished | Aug 14 04:19:36 PM PDT 24 |
| Peak memory | 146600 kb |
| Host | smart-0fb35b41-f377-4bcd-8400-2689210fa22d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2559511446 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2559511446 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.245214618 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4948496 ps |
| CPU time | 0.39 seconds |
| Started | Aug 14 04:19:41 PM PDT 24 |
| Finished | Aug 14 04:19:42 PM PDT 24 |
| Peak memory | 147244 kb |
| Host | smart-eea20240-5030-4cb1-b275-240fa0b10763 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=245214618 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.245214618 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.3752425154 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5050826 ps |
| CPU time | 0.39 seconds |
| Started | Aug 14 04:19:29 PM PDT 24 |
| Finished | Aug 14 04:19:29 PM PDT 24 |
| Peak memory | 145196 kb |
| Host | smart-45ba0d16-b046-454c-abd0-c8d7caa0c2f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752425154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.3752425154 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.3206453781 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4913938 ps |
| CPU time | 0.38 seconds |
| Started | Aug 14 04:25:09 PM PDT 24 |
| Finished | Aug 14 04:25:09 PM PDT 24 |
| Peak memory | 146068 kb |
| Host | smart-57adc3e5-b72b-4394-8691-e08f466fcc60 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206453781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3206453781 |
| Directory | /workspace/8.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |