Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.29 95.41 87.80 100.00 96.43 88.89 85.19


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.33 87.33 92.66 92.66 85.37 85.37 100.00 100.00 78.57 78.57 82.22 82.22 85.19 85.19 /workspace/coverage/default/16.prim_esc_test.2510579248
90.05 2.72 93.58 0.92 87.80 2.44 100.00 0.00 89.29 10.71 84.44 2.22 85.19 0.00 /workspace/coverage/default/5.prim_esc_test.1985342627
91.17 1.12 94.50 0.92 87.80 0.00 100.00 0.00 92.86 3.57 86.67 2.22 85.19 0.00 /workspace/coverage/default/1.prim_esc_test.684934065
92.29 1.12 95.41 0.92 87.80 0.00 100.00 0.00 96.43 3.57 88.89 2.22 85.19 0.00 /workspace/coverage/default/11.prim_esc_test.2074711624

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.prim_esc_test.2646647743
/workspace/coverage/default/10.prim_esc_test.1812621332
/workspace/coverage/default/12.prim_esc_test.2223412743
/workspace/coverage/default/13.prim_esc_test.941899399
/workspace/coverage/default/14.prim_esc_test.582779972
/workspace/coverage/default/15.prim_esc_test.2263045179
/workspace/coverage/default/17.prim_esc_test.746172633
/workspace/coverage/default/18.prim_esc_test.3106956966
/workspace/coverage/default/19.prim_esc_test.1971837425
/workspace/coverage/default/2.prim_esc_test.3887926615
/workspace/coverage/default/3.prim_esc_test.3084786090
/workspace/coverage/default/4.prim_esc_test.3951690719
/workspace/coverage/default/6.prim_esc_test.1643473854
/workspace/coverage/default/7.prim_esc_test.635073447
/workspace/coverage/default/8.prim_esc_test.3968916519
/workspace/coverage/default/9.prim_esc_test.178390137



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/1.prim_esc_test.684934065 Aug 15 05:22:07 PM PDT 24 Aug 15 05:22:07 PM PDT 24 4416315 ps
T2 /workspace/coverage/default/3.prim_esc_test.3084786090 Aug 15 05:21:39 PM PDT 24 Aug 15 05:21:39 PM PDT 24 4727401 ps
T3 /workspace/coverage/default/0.prim_esc_test.2646647743 Aug 15 05:22:07 PM PDT 24 Aug 15 05:22:08 PM PDT 24 5529586 ps
T7 /workspace/coverage/default/18.prim_esc_test.3106956966 Aug 15 05:21:38 PM PDT 24 Aug 15 05:21:39 PM PDT 24 4760670 ps
T8 /workspace/coverage/default/16.prim_esc_test.2510579248 Aug 15 05:22:05 PM PDT 24 Aug 15 05:22:05 PM PDT 24 4732401 ps
T4 /workspace/coverage/default/2.prim_esc_test.3887926615 Aug 15 05:21:55 PM PDT 24 Aug 15 05:21:56 PM PDT 24 4787043 ps
T5 /workspace/coverage/default/19.prim_esc_test.1971837425 Aug 15 05:21:58 PM PDT 24 Aug 15 05:21:58 PM PDT 24 5035828 ps
T6 /workspace/coverage/default/7.prim_esc_test.635073447 Aug 15 05:21:53 PM PDT 24 Aug 15 05:21:54 PM PDT 24 4375396 ps
T12 /workspace/coverage/default/9.prim_esc_test.178390137 Aug 15 05:21:47 PM PDT 24 Aug 15 05:21:48 PM PDT 24 5535675 ps
T13 /workspace/coverage/default/13.prim_esc_test.941899399 Aug 15 05:21:52 PM PDT 24 Aug 15 05:21:53 PM PDT 24 4760963 ps
T16 /workspace/coverage/default/12.prim_esc_test.2223412743 Aug 15 05:22:07 PM PDT 24 Aug 15 05:22:08 PM PDT 24 5081995 ps
T14 /workspace/coverage/default/11.prim_esc_test.2074711624 Aug 15 05:21:53 PM PDT 24 Aug 15 05:21:53 PM PDT 24 4384556 ps
T9 /workspace/coverage/default/5.prim_esc_test.1985342627 Aug 15 05:22:03 PM PDT 24 Aug 15 05:22:03 PM PDT 24 4856931 ps
T10 /workspace/coverage/default/10.prim_esc_test.1812621332 Aug 15 05:21:49 PM PDT 24 Aug 15 05:21:50 PM PDT 24 4707880 ps
T17 /workspace/coverage/default/8.prim_esc_test.3968916519 Aug 15 05:22:02 PM PDT 24 Aug 15 05:22:02 PM PDT 24 5080857 ps
T11 /workspace/coverage/default/14.prim_esc_test.582779972 Aug 15 05:22:12 PM PDT 24 Aug 15 05:22:13 PM PDT 24 4988350 ps
T18 /workspace/coverage/default/4.prim_esc_test.3951690719 Aug 15 05:21:59 PM PDT 24 Aug 15 05:21:59 PM PDT 24 4985205 ps
T15 /workspace/coverage/default/15.prim_esc_test.2263045179 Aug 15 05:21:55 PM PDT 24 Aug 15 05:21:56 PM PDT 24 4721745 ps
T19 /workspace/coverage/default/6.prim_esc_test.1643473854 Aug 15 05:21:54 PM PDT 24 Aug 15 05:21:54 PM PDT 24 4983625 ps
T20 /workspace/coverage/default/17.prim_esc_test.746172633 Aug 15 05:21:54 PM PDT 24 Aug 15 05:21:55 PM PDT 24 5169483 ps

Test location /workspace/coverage/default/16.prim_esc_test.2510579248
Short name T8
Test name
Test status
Simulation time 4732401 ps
CPU time 0.38 seconds
Started Aug 15 05:22:05 PM PDT 24
Finished Aug 15 05:22:05 PM PDT 24
Peak memory 146504 kb
Host smart-03550dc0-2ce7-41c3-b338-a50b75e98433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510579248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.2510579248
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.1985342627
Short name T9
Test name
Test status
Simulation time 4856931 ps
CPU time 0.4 seconds
Started Aug 15 05:22:03 PM PDT 24
Finished Aug 15 05:22:03 PM PDT 24
Peak memory 146456 kb
Host smart-90dee6b1-3f6f-4476-b9cf-970567d7e03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985342627 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1985342627
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.684934065
Short name T1
Test name
Test status
Simulation time 4416315 ps
CPU time 0.39 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:07 PM PDT 24
Peak memory 146484 kb
Host smart-1186d91b-2ae2-4d61-91c5-c463182dbf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684934065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.684934065
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.2074711624
Short name T14
Test name
Test status
Simulation time 4384556 ps
CPU time 0.37 seconds
Started Aug 15 05:21:53 PM PDT 24
Finished Aug 15 05:21:53 PM PDT 24
Peak memory 146504 kb
Host smart-725cec64-44b8-437b-b79d-566a66cc5e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074711624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2074711624
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.2646647743
Short name T3
Test name
Test status
Simulation time 5529586 ps
CPU time 0.38 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:08 PM PDT 24
Peak memory 146508 kb
Host smart-58f7813d-4428-486c-b93b-7ed93e757b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646647743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2646647743
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.1812621332
Short name T10
Test name
Test status
Simulation time 4707880 ps
CPU time 0.39 seconds
Started Aug 15 05:21:49 PM PDT 24
Finished Aug 15 05:21:50 PM PDT 24
Peak memory 146488 kb
Host smart-4b449247-e91e-4c32-a3ad-4a9982555407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812621332 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.1812621332
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.2223412743
Short name T16
Test name
Test status
Simulation time 5081995 ps
CPU time 0.38 seconds
Started Aug 15 05:22:07 PM PDT 24
Finished Aug 15 05:22:08 PM PDT 24
Peak memory 146508 kb
Host smart-1d1a8ffb-f67f-4c73-9457-9fd5c97bf92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223412743 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2223412743
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.941899399
Short name T13
Test name
Test status
Simulation time 4760963 ps
CPU time 0.38 seconds
Started Aug 15 05:21:52 PM PDT 24
Finished Aug 15 05:21:53 PM PDT 24
Peak memory 146512 kb
Host smart-c305ddcf-2902-465b-96a7-0fac7cd5f243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941899399 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.941899399
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.582779972
Short name T11
Test name
Test status
Simulation time 4988350 ps
CPU time 0.38 seconds
Started Aug 15 05:22:12 PM PDT 24
Finished Aug 15 05:22:13 PM PDT 24
Peak memory 146500 kb
Host smart-0576226e-758f-4088-ae96-65a0bfd4f101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582779972 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.582779972
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.2263045179
Short name T15
Test name
Test status
Simulation time 4721745 ps
CPU time 0.36 seconds
Started Aug 15 05:21:55 PM PDT 24
Finished Aug 15 05:21:56 PM PDT 24
Peak memory 146496 kb
Host smart-a49a2107-519e-4879-a26b-c9f8f70ac252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263045179 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2263045179
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.746172633
Short name T20
Test name
Test status
Simulation time 5169483 ps
CPU time 0.37 seconds
Started Aug 15 05:21:54 PM PDT 24
Finished Aug 15 05:21:55 PM PDT 24
Peak memory 146476 kb
Host smart-f986e3c3-a1bf-475b-8e08-7f94ed9d2f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746172633 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.746172633
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/18.prim_esc_test.3106956966
Short name T7
Test name
Test status
Simulation time 4760670 ps
CPU time 0.38 seconds
Started Aug 15 05:21:38 PM PDT 24
Finished Aug 15 05:21:39 PM PDT 24
Peak memory 146488 kb
Host smart-7e0068ef-91b5-4132-8e32-71835ffb4e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106956966 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3106956966
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.1971837425
Short name T5
Test name
Test status
Simulation time 5035828 ps
CPU time 0.39 seconds
Started Aug 15 05:21:58 PM PDT 24
Finished Aug 15 05:21:58 PM PDT 24
Peak memory 146456 kb
Host smart-467b81d5-c8af-4ce0-be36-5056681e9119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971837425 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.1971837425
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.3887926615
Short name T4
Test name
Test status
Simulation time 4787043 ps
CPU time 0.38 seconds
Started Aug 15 05:21:55 PM PDT 24
Finished Aug 15 05:21:56 PM PDT 24
Peak memory 146428 kb
Host smart-55175ffb-39c2-4252-a2f4-e7a43a77b2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887926615 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.3887926615
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.3084786090
Short name T2
Test name
Test status
Simulation time 4727401 ps
CPU time 0.37 seconds
Started Aug 15 05:21:39 PM PDT 24
Finished Aug 15 05:21:39 PM PDT 24
Peak memory 146404 kb
Host smart-ac8a4b47-f940-425e-be04-a8500592a321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084786090 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3084786090
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.3951690719
Short name T18
Test name
Test status
Simulation time 4985205 ps
CPU time 0.37 seconds
Started Aug 15 05:21:59 PM PDT 24
Finished Aug 15 05:21:59 PM PDT 24
Peak memory 146472 kb
Host smart-0d6ef1e6-616c-49c5-9bb2-642b54c3c409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951690719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.3951690719
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.1643473854
Short name T19
Test name
Test status
Simulation time 4983625 ps
CPU time 0.43 seconds
Started Aug 15 05:21:54 PM PDT 24
Finished Aug 15 05:21:54 PM PDT 24
Peak memory 146496 kb
Host smart-7bcb175b-9968-4b07-b67c-d7221c3cd319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643473854 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.1643473854
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.635073447
Short name T6
Test name
Test status
Simulation time 4375396 ps
CPU time 0.38 seconds
Started Aug 15 05:21:53 PM PDT 24
Finished Aug 15 05:21:54 PM PDT 24
Peak memory 146400 kb
Host smart-46677f30-d168-4be0-bf55-12430d087ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635073447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.635073447
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.3968916519
Short name T17
Test name
Test status
Simulation time 5080857 ps
CPU time 0.42 seconds
Started Aug 15 05:22:02 PM PDT 24
Finished Aug 15 05:22:02 PM PDT 24
Peak memory 146508 kb
Host smart-0fcd7656-7467-4857-bc06-c7b2cf1ba41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968916519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.3968916519
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.178390137
Short name T12
Test name
Test status
Simulation time 5535675 ps
CPU time 0.38 seconds
Started Aug 15 05:21:47 PM PDT 24
Finished Aug 15 05:21:48 PM PDT 24
Peak memory 146512 kb
Host smart-28e23747-7c96-402c-8651-368f5c1d4a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178390137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.178390137
Directory /workspace/9.prim_esc_test/latest
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