| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/3.prim_esc_test.2751493121 |
| 89.45 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/19.prim_esc_test.3960270306 |
| 91.17 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/11.prim_esc_test.2202121668 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/12.prim_esc_test.2815817901 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1401829793 |
| /workspace/coverage/default/1.prim_esc_test.3620979766 |
| /workspace/coverage/default/10.prim_esc_test.2525512243 |
| /workspace/coverage/default/13.prim_esc_test.2933651072 |
| /workspace/coverage/default/14.prim_esc_test.3348737231 |
| /workspace/coverage/default/15.prim_esc_test.1326892134 |
| /workspace/coverage/default/16.prim_esc_test.1322118666 |
| /workspace/coverage/default/17.prim_esc_test.3325671015 |
| /workspace/coverage/default/18.prim_esc_test.3617755322 |
| /workspace/coverage/default/2.prim_esc_test.1062875235 |
| /workspace/coverage/default/4.prim_esc_test.1989042936 |
| /workspace/coverage/default/5.prim_esc_test.1053500662 |
| /workspace/coverage/default/6.prim_esc_test.2412811519 |
| /workspace/coverage/default/7.prim_esc_test.396985640 |
| /workspace/coverage/default/8.prim_esc_test.349192183 |
| /workspace/coverage/default/9.prim_esc_test.2053848870 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/14.prim_esc_test.3348737231 | Aug 16 04:25:31 PM PDT 24 | Aug 16 04:25:32 PM PDT 24 | 4680410 ps | ||
| T2 | /workspace/coverage/default/17.prim_esc_test.3325671015 | Aug 16 04:25:21 PM PDT 24 | Aug 16 04:25:22 PM PDT 24 | 4166673 ps | ||
| T3 | /workspace/coverage/default/18.prim_esc_test.3617755322 | Aug 16 04:25:29 PM PDT 24 | Aug 16 04:25:30 PM PDT 24 | 4528275 ps | ||
| T4 | /workspace/coverage/default/3.prim_esc_test.2751493121 | Aug 16 04:23:58 PM PDT 24 | Aug 16 04:23:58 PM PDT 24 | 5333149 ps | ||
| T5 | /workspace/coverage/default/0.prim_esc_test.1401829793 | Aug 16 04:19:29 PM PDT 24 | Aug 16 04:19:30 PM PDT 24 | 4553385 ps | ||
| T6 | /workspace/coverage/default/2.prim_esc_test.1062875235 | Aug 16 04:20:56 PM PDT 24 | Aug 16 04:20:57 PM PDT 24 | 4716353 ps | ||
| T13 | /workspace/coverage/default/8.prim_esc_test.349192183 | Aug 16 04:20:25 PM PDT 24 | Aug 16 04:20:26 PM PDT 24 | 4889243 ps | ||
| T8 | /workspace/coverage/default/16.prim_esc_test.1322118666 | Aug 16 04:25:18 PM PDT 24 | Aug 16 04:25:29 PM PDT 24 | 5181899 ps | ||
| T7 | /workspace/coverage/default/13.prim_esc_test.2933651072 | Aug 16 04:25:22 PM PDT 24 | Aug 16 04:25:22 PM PDT 24 | 4803131 ps | ||
| T9 | /workspace/coverage/default/15.prim_esc_test.1326892134 | Aug 16 04:25:37 PM PDT 24 | Aug 16 04:25:37 PM PDT 24 | 4737823 ps | ||
| T10 | /workspace/coverage/default/9.prim_esc_test.2053848870 | Aug 16 04:22:32 PM PDT 24 | Aug 16 04:22:32 PM PDT 24 | 5303135 ps | ||
| T11 | /workspace/coverage/default/19.prim_esc_test.3960270306 | Aug 16 04:25:34 PM PDT 24 | Aug 16 04:25:35 PM PDT 24 | 5168638 ps | ||
| T14 | /workspace/coverage/default/10.prim_esc_test.2525512243 | Aug 16 04:25:19 PM PDT 24 | Aug 16 04:25:20 PM PDT 24 | 4756098 ps | ||
| T16 | /workspace/coverage/default/6.prim_esc_test.2412811519 | Aug 16 04:22:55 PM PDT 24 | Aug 16 04:22:55 PM PDT 24 | 5111518 ps | ||
| T17 | /workspace/coverage/default/5.prim_esc_test.1053500662 | Aug 16 04:20:13 PM PDT 24 | Aug 16 04:20:13 PM PDT 24 | 4555981 ps | ||
| T18 | /workspace/coverage/default/4.prim_esc_test.1989042936 | Aug 16 04:21:14 PM PDT 24 | Aug 16 04:21:14 PM PDT 24 | 4999566 ps | ||
| T15 | /workspace/coverage/default/12.prim_esc_test.2815817901 | Aug 16 04:25:22 PM PDT 24 | Aug 16 04:25:22 PM PDT 24 | 4919616 ps | ||
| T19 | /workspace/coverage/default/7.prim_esc_test.396985640 | Aug 16 04:20:25 PM PDT 24 | Aug 16 04:20:26 PM PDT 24 | 4925650 ps | ||
| T20 | /workspace/coverage/default/11.prim_esc_test.2202121668 | Aug 16 04:25:30 PM PDT 24 | Aug 16 04:25:35 PM PDT 24 | 5273196 ps | ||
| T12 | /workspace/coverage/default/1.prim_esc_test.3620979766 | Aug 16 04:20:34 PM PDT 24 | Aug 16 04:20:35 PM PDT 24 | 5025423 ps |
| Test location | /workspace/coverage/default/3.prim_esc_test.2751493121 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5333149 ps |
| CPU time | 0.37 seconds |
| Started | Aug 16 04:23:58 PM PDT 24 |
| Finished | Aug 16 04:23:58 PM PDT 24 |
| Peak memory | 147160 kb |
| Host | smart-dc8f5ce7-cd50-4bd3-b75d-088fa45ebb3e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2751493121 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.2751493121 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.3960270306 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5168638 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 04:25:34 PM PDT 24 |
| Finished | Aug 16 04:25:35 PM PDT 24 |
| Peak memory | 146256 kb |
| Host | smart-03f36143-b4c4-479f-a369-339bfc6e88e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3960270306 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.3960270306 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/11.prim_esc_test.2202121668 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5273196 ps |
| CPU time | 0.37 seconds |
| Started | Aug 16 04:25:30 PM PDT 24 |
| Finished | Aug 16 04:25:35 PM PDT 24 |
| Peak memory | 146252 kb |
| Host | smart-41f88177-c941-4b29-85ba-927c2cafad9e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202121668 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2202121668 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2815817901 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4919616 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 04:25:22 PM PDT 24 |
| Finished | Aug 16 04:25:22 PM PDT 24 |
| Peak memory | 146112 kb |
| Host | smart-8bc088ab-1a9a-47a9-973f-2cd1639c6eb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815817901 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2815817901 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1401829793 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4553385 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 04:19:29 PM PDT 24 |
| Finished | Aug 16 04:19:30 PM PDT 24 |
| Peak memory | 146384 kb |
| Host | smart-76af23c7-1af9-4bf3-a329-f814f278ff44 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1401829793 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1401829793 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.3620979766 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5025423 ps |
| CPU time | 0.42 seconds |
| Started | Aug 16 04:20:34 PM PDT 24 |
| Finished | Aug 16 04:20:35 PM PDT 24 |
| Peak memory | 146480 kb |
| Host | smart-f60163ac-329c-4c35-b5a9-0c33fd275eef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3620979766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.3620979766 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2525512243 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4756098 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 04:25:19 PM PDT 24 |
| Finished | Aug 16 04:25:20 PM PDT 24 |
| Peak memory | 146248 kb |
| Host | smart-02487dd4-5080-4489-a0d4-a1f960892eb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525512243 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2525512243 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2933651072 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4803131 ps |
| CPU time | 0.37 seconds |
| Started | Aug 16 04:25:22 PM PDT 24 |
| Finished | Aug 16 04:25:22 PM PDT 24 |
| Peak memory | 146284 kb |
| Host | smart-b3228208-914a-42ac-9489-0f87bc320d01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2933651072 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2933651072 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.3348737231 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4680410 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 04:25:31 PM PDT 24 |
| Finished | Aug 16 04:25:32 PM PDT 24 |
| Peak memory | 145996 kb |
| Host | smart-34a6f7dd-77bc-4745-bcb5-270eb0829d11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348737231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3348737231 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1326892134 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4737823 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 04:25:37 PM PDT 24 |
| Finished | Aug 16 04:25:37 PM PDT 24 |
| Peak memory | 146028 kb |
| Host | smart-15cec73a-f1cc-4522-ba23-aa58c9adca05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1326892134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1326892134 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.1322118666 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5181899 ps |
| CPU time | 0.37 seconds |
| Started | Aug 16 04:25:18 PM PDT 24 |
| Finished | Aug 16 04:25:29 PM PDT 24 |
| Peak memory | 146020 kb |
| Host | smart-ec182a41-7932-4da0-9b12-b13ce4ea9b53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1322118666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.1322118666 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.3325671015 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4166673 ps |
| CPU time | 0.42 seconds |
| Started | Aug 16 04:25:21 PM PDT 24 |
| Finished | Aug 16 04:25:22 PM PDT 24 |
| Peak memory | 146092 kb |
| Host | smart-04aff5b4-07a2-452f-917c-1513d56926e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3325671015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.3325671015 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3617755322 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4528275 ps |
| CPU time | 0.37 seconds |
| Started | Aug 16 04:25:29 PM PDT 24 |
| Finished | Aug 16 04:25:30 PM PDT 24 |
| Peak memory | 146284 kb |
| Host | smart-4ca10123-38dd-421f-8651-4af1ff5713c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3617755322 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3617755322 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1062875235 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4716353 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 04:20:56 PM PDT 24 |
| Finished | Aug 16 04:20:57 PM PDT 24 |
| Peak memory | 146252 kb |
| Host | smart-0f99a69c-eacf-44b3-a0f6-01fe5d70d3b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1062875235 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1062875235 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.1989042936 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4999566 ps |
| CPU time | 0.39 seconds |
| Started | Aug 16 04:21:14 PM PDT 24 |
| Finished | Aug 16 04:21:14 PM PDT 24 |
| Peak memory | 146480 kb |
| Host | smart-9d34c149-5ce9-4d2f-825d-2b2752a4409a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1989042936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.1989042936 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.1053500662 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4555981 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 04:20:13 PM PDT 24 |
| Finished | Aug 16 04:20:13 PM PDT 24 |
| Peak memory | 146480 kb |
| Host | smart-b52a759d-cd23-454a-b3b4-4c71ffc5c173 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1053500662 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.1053500662 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.2412811519 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5111518 ps |
| CPU time | 0.36 seconds |
| Started | Aug 16 04:22:55 PM PDT 24 |
| Finished | Aug 16 04:22:55 PM PDT 24 |
| Peak memory | 146880 kb |
| Host | smart-839ebbf3-2208-4b76-a73b-c7c6437afd8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2412811519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.2412811519 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.396985640 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4925650 ps |
| CPU time | 0.4 seconds |
| Started | Aug 16 04:20:25 PM PDT 24 |
| Finished | Aug 16 04:20:26 PM PDT 24 |
| Peak memory | 146124 kb |
| Host | smart-9196c2ff-ba92-43e8-94c5-e00c4808c589 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=396985640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.396985640 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.349192183 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4889243 ps |
| CPU time | 0.43 seconds |
| Started | Aug 16 04:20:25 PM PDT 24 |
| Finished | Aug 16 04:20:26 PM PDT 24 |
| Peak memory | 146112 kb |
| Host | smart-815b131f-4012-4c32-9939-0b7e766bda1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=349192183 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.349192183 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2053848870 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5303135 ps |
| CPU time | 0.38 seconds |
| Started | Aug 16 04:22:32 PM PDT 24 |
| Finished | Aug 16 04:22:32 PM PDT 24 |
| Peak memory | 146176 kb |
| Host | smart-b0d85ee0-aeeb-49dd-9870-14a2182f0a70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053848870 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2053848870 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |