| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.33 | 87.33 | 92.66 | 92.66 | 85.37 | 85.37 | 100.00 | 100.00 | 78.57 | 78.57 | 82.22 | 82.22 | 85.19 | 85.19 | /workspace/coverage/default/11.prim_esc_test.1415432405 |
| 89.45 | 2.12 | 93.58 | 0.92 | 87.80 | 2.44 | 100.00 | 0.00 | 85.71 | 7.14 | 84.44 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/16.prim_esc_test.4080644766 |
| 90.57 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/1.prim_esc_test.4167883363 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/15.prim_esc_test.1705241551 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspace/coverage/default/18.prim_esc_test.3575194559 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.1078607912 |
| /workspace/coverage/default/10.prim_esc_test.421521808 |
| /workspace/coverage/default/12.prim_esc_test.2396964719 |
| /workspace/coverage/default/13.prim_esc_test.2621238737 |
| /workspace/coverage/default/14.prim_esc_test.2009861892 |
| /workspace/coverage/default/17.prim_esc_test.1499012811 |
| /workspace/coverage/default/19.prim_esc_test.2128782353 |
| /workspace/coverage/default/2.prim_esc_test.1510423686 |
| /workspace/coverage/default/3.prim_esc_test.1594076187 |
| /workspace/coverage/default/4.prim_esc_test.2832352619 |
| /workspace/coverage/default/5.prim_esc_test.3825094363 |
| /workspace/coverage/default/6.prim_esc_test.977135201 |
| /workspace/coverage/default/7.prim_esc_test.95968173 |
| /workspace/coverage/default/8.prim_esc_test.1817213035 |
| /workspace/coverage/default/9.prim_esc_test.2917053944 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/12.prim_esc_test.2396964719 | Aug 17 04:20:27 PM PDT 24 | Aug 17 04:20:28 PM PDT 24 | 4804879 ps | ||
| T2 | /workspace/coverage/default/8.prim_esc_test.1817213035 | Aug 17 04:25:13 PM PDT 24 | Aug 17 04:25:14 PM PDT 24 | 4947586 ps | ||
| T3 | /workspace/coverage/default/6.prim_esc_test.977135201 | Aug 17 04:25:26 PM PDT 24 | Aug 17 04:25:27 PM PDT 24 | 5162091 ps | ||
| T7 | /workspace/coverage/default/4.prim_esc_test.2832352619 | Aug 17 04:22:06 PM PDT 24 | Aug 17 04:22:06 PM PDT 24 | 4824100 ps | ||
| T8 | /workspace/coverage/default/3.prim_esc_test.1594076187 | Aug 17 04:24:53 PM PDT 24 | Aug 17 04:24:54 PM PDT 24 | 5101113 ps | ||
| T4 | /workspace/coverage/default/5.prim_esc_test.3825094363 | Aug 17 04:24:53 PM PDT 24 | Aug 17 04:24:53 PM PDT 24 | 4896831 ps | ||
| T9 | /workspace/coverage/default/11.prim_esc_test.1415432405 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:20:27 PM PDT 24 | 4608392 ps | ||
| T10 | /workspace/coverage/default/10.prim_esc_test.421521808 | Aug 17 04:25:14 PM PDT 24 | Aug 17 04:25:15 PM PDT 24 | 4983239 ps | ||
| T13 | /workspace/coverage/default/15.prim_esc_test.1705241551 | Aug 17 04:21:27 PM PDT 24 | Aug 17 04:21:28 PM PDT 24 | 4528867 ps | ||
| T5 | /workspace/coverage/default/14.prim_esc_test.2009861892 | Aug 17 04:21:40 PM PDT 24 | Aug 17 04:21:40 PM PDT 24 | 4716562 ps | ||
| T12 | /workspace/coverage/default/19.prim_esc_test.2128782353 | Aug 17 04:20:25 PM PDT 24 | Aug 17 04:20:26 PM PDT 24 | 4767794 ps | ||
| T6 | /workspace/coverage/default/0.prim_esc_test.1078607912 | Aug 17 04:22:04 PM PDT 24 | Aug 17 04:22:05 PM PDT 24 | 5692688 ps | ||
| T14 | /workspace/coverage/default/7.prim_esc_test.95968173 | Aug 17 04:25:11 PM PDT 24 | Aug 17 04:25:12 PM PDT 24 | 4914774 ps | ||
| T18 | /workspace/coverage/default/13.prim_esc_test.2621238737 | Aug 17 04:21:41 PM PDT 24 | Aug 17 04:21:41 PM PDT 24 | 4845707 ps | ||
| T15 | /workspace/coverage/default/9.prim_esc_test.2917053944 | Aug 17 04:21:36 PM PDT 24 | Aug 17 04:21:37 PM PDT 24 | 4735986 ps | ||
| T16 | /workspace/coverage/default/1.prim_esc_test.4167883363 | Aug 17 04:25:46 PM PDT 24 | Aug 17 04:25:47 PM PDT 24 | 4433124 ps | ||
| T19 | /workspace/coverage/default/17.prim_esc_test.1499012811 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:20:27 PM PDT 24 | 4687129 ps | ||
| T17 | /workspace/coverage/default/18.prim_esc_test.3575194559 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:20:26 PM PDT 24 | 4305979 ps | ||
| T20 | /workspace/coverage/default/16.prim_esc_test.4080644766 | Aug 17 04:20:26 PM PDT 24 | Aug 17 04:20:27 PM PDT 24 | 5331273 ps | ||
| T11 | /workspace/coverage/default/2.prim_esc_test.1510423686 | Aug 17 04:25:07 PM PDT 24 | Aug 17 04:25:08 PM PDT 24 | 4389534 ps |
| Test location | /workspace/coverage/default/11.prim_esc_test.1415432405 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4608392 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 04:20:26 PM PDT 24 |
| Finished | Aug 17 04:20:27 PM PDT 24 |
| Peak memory | 146620 kb |
| Host | smart-7df1ab54-31f7-4737-a397-d2f8b1e2f140 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415432405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.1415432405 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.4080644766 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5331273 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:20:26 PM PDT 24 |
| Finished | Aug 17 04:20:27 PM PDT 24 |
| Peak memory | 146240 kb |
| Host | smart-35474860-823d-4006-8dba-5ea5682fb16d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4080644766 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.4080644766 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.4167883363 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4433124 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:25:46 PM PDT 24 |
| Finished | Aug 17 04:25:47 PM PDT 24 |
| Peak memory | 146392 kb |
| Host | smart-19cab854-691f-47be-819b-d306241b5509 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4167883363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.4167883363 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.1705241551 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4528867 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:21:27 PM PDT 24 |
| Finished | Aug 17 04:21:28 PM PDT 24 |
| Peak memory | 145256 kb |
| Host | smart-9567f921-dbf6-4ca3-b6a4-d2b8f8155dbf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1705241551 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.1705241551 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.3575194559 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4305979 ps |
| CPU time | 0.37 seconds |
| Started | Aug 17 04:20:26 PM PDT 24 |
| Finished | Aug 17 04:20:26 PM PDT 24 |
| Peak memory | 147004 kb |
| Host | smart-06bf3e29-cdbb-4570-8603-73f7fd813864 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3575194559 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.3575194559 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.1078607912 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5692688 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:22:04 PM PDT 24 |
| Finished | Aug 17 04:22:05 PM PDT 24 |
| Peak memory | 146256 kb |
| Host | smart-dc684601-7562-4e3b-aff9-a0eae10ecf43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078607912 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.1078607912 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.421521808 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4983239 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 04:25:14 PM PDT 24 |
| Finished | Aug 17 04:25:15 PM PDT 24 |
| Peak memory | 145940 kb |
| Host | smart-0c74c680-3105-4d27-8391-b70e781a26cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=421521808 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.421521808 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.2396964719 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4804879 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:20:27 PM PDT 24 |
| Finished | Aug 17 04:20:28 PM PDT 24 |
| Peak memory | 146620 kb |
| Host | smart-42d4c644-95ab-40e5-a32d-482c2d81e4d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2396964719 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.2396964719 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.2621238737 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4845707 ps |
| CPU time | 0.37 seconds |
| Started | Aug 17 04:21:41 PM PDT 24 |
| Finished | Aug 17 04:21:41 PM PDT 24 |
| Peak memory | 146224 kb |
| Host | smart-871b6461-534a-41c4-a610-27570e6c1ff5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2621238737 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2621238737 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.2009861892 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4716562 ps |
| CPU time | 0.37 seconds |
| Started | Aug 17 04:21:40 PM PDT 24 |
| Finished | Aug 17 04:21:40 PM PDT 24 |
| Peak memory | 146128 kb |
| Host | smart-66977f87-e58b-425e-bb63-5b3c7fc480d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2009861892 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.2009861892 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.1499012811 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4687129 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 04:20:26 PM PDT 24 |
| Finished | Aug 17 04:20:27 PM PDT 24 |
| Peak memory | 147176 kb |
| Host | smart-1f582f22-7b28-4782-aeac-dda6bb785c87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1499012811 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1499012811 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.2128782353 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4767794 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:20:25 PM PDT 24 |
| Finished | Aug 17 04:20:26 PM PDT 24 |
| Peak memory | 146308 kb |
| Host | smart-02833f6f-1dd2-47b9-b72b-ec4faf8ef521 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2128782353 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2128782353 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.1510423686 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4389534 ps |
| CPU time | 0.37 seconds |
| Started | Aug 17 04:25:07 PM PDT 24 |
| Finished | Aug 17 04:25:08 PM PDT 24 |
| Peak memory | 146008 kb |
| Host | smart-763395c6-5d39-48af-83bb-7e2ae7a1d209 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1510423686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.1510423686 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1594076187 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5101113 ps |
| CPU time | 0.41 seconds |
| Started | Aug 17 04:24:53 PM PDT 24 |
| Finished | Aug 17 04:24:54 PM PDT 24 |
| Peak memory | 145816 kb |
| Host | smart-7aa4f2a5-a97a-4169-af26-f1ed92cb81c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594076187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1594076187 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2832352619 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4824100 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:22:06 PM PDT 24 |
| Finished | Aug 17 04:22:06 PM PDT 24 |
| Peak memory | 146256 kb |
| Host | smart-c680a373-aa9c-4dc9-a169-dfa07f1bdf5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2832352619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2832352619 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.3825094363 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4896831 ps |
| CPU time | 0.39 seconds |
| Started | Aug 17 04:24:53 PM PDT 24 |
| Finished | Aug 17 04:24:53 PM PDT 24 |
| Peak memory | 146252 kb |
| Host | smart-44d4df5e-de22-4657-935b-bc51c1f1a7dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3825094363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.3825094363 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.977135201 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5162091 ps |
| CPU time | 0.42 seconds |
| Started | Aug 17 04:25:26 PM PDT 24 |
| Finished | Aug 17 04:25:27 PM PDT 24 |
| Peak memory | 146056 kb |
| Host | smart-0f99590f-024f-43b8-bf51-645abbbb459a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=977135201 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.977135201 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.95968173 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4914774 ps |
| CPU time | 0.36 seconds |
| Started | Aug 17 04:25:11 PM PDT 24 |
| Finished | Aug 17 04:25:12 PM PDT 24 |
| Peak memory | 147124 kb |
| Host | smart-44d842ce-b5ab-4bda-adb9-059cb8753f5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=95968173 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.95968173 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.1817213035 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4947586 ps |
| CPU time | 0.41 seconds |
| Started | Aug 17 04:25:13 PM PDT 24 |
| Finished | Aug 17 04:25:14 PM PDT 24 |
| Peak memory | 146312 kb |
| Host | smart-10df13d7-0404-48d3-9691-6e58a160e2da |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1817213035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.1817213035 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.2917053944 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4735986 ps |
| CPU time | 0.38 seconds |
| Started | Aug 17 04:21:36 PM PDT 24 |
| Finished | Aug 17 04:21:37 PM PDT 24 |
| Peak memory | 146324 kb |
| Host | smart-9fc34b6f-509a-46e7-8927-3603b8d0d76b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2917053944 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.2917053944 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |