| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 85.66 | 85.66 | 90.83 | 90.83 | 82.93 | 82.93 | 100.00 | 100.00 | 75.00 | 75.00 | 80.00 | 80.00 | 85.19 | 85.19 | /workspace/coverage/default/11.prim_esc_test.307958558 |
| 88.86 | 3.20 | 93.58 | 2.75 | 87.80 | 4.88 | 100.00 | 0.00 | 82.14 | 7.14 | 84.44 | 4.44 | 85.19 | 0.00 | /workspace/coverage/default/14.prim_esc_test.1919256971 |
| 90.57 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/7.prim_esc_test.1907938098 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspace/coverage/default/10.prim_esc_test.2135061625 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspace/coverage/default/13.prim_esc_test.4085059865 |
| Name |
|---|
| /workspace/coverage/default/0.prim_esc_test.2314247441 |
| /workspace/coverage/default/1.prim_esc_test.1776204643 |
| /workspace/coverage/default/12.prim_esc_test.3755881981 |
| /workspace/coverage/default/15.prim_esc_test.3771501558 |
| /workspace/coverage/default/16.prim_esc_test.3112855678 |
| /workspace/coverage/default/17.prim_esc_test.2222276555 |
| /workspace/coverage/default/18.prim_esc_test.545277363 |
| /workspace/coverage/default/19.prim_esc_test.505022193 |
| /workspace/coverage/default/2.prim_esc_test.2626914585 |
| /workspace/coverage/default/3.prim_esc_test.1764670652 |
| /workspace/coverage/default/4.prim_esc_test.2612761909 |
| /workspace/coverage/default/5.prim_esc_test.502470215 |
| /workspace/coverage/default/6.prim_esc_test.4033483124 |
| /workspace/coverage/default/8.prim_esc_test.853584411 |
| /workspace/coverage/default/9.prim_esc_test.3872770608 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/17.prim_esc_test.2222276555 | Aug 18 04:21:44 PM PDT 24 | Aug 18 04:21:45 PM PDT 24 | 5285627 ps | ||
| T2 | /workspace/coverage/default/0.prim_esc_test.2314247441 | Aug 18 04:17:12 PM PDT 24 | Aug 18 04:17:12 PM PDT 24 | 4490546 ps | ||
| T3 | /workspace/coverage/default/13.prim_esc_test.4085059865 | Aug 18 04:21:45 PM PDT 24 | Aug 18 04:21:46 PM PDT 24 | 5069767 ps | ||
| T4 | /workspace/coverage/default/7.prim_esc_test.1907938098 | Aug 18 04:22:30 PM PDT 24 | Aug 18 04:22:31 PM PDT 24 | 4891482 ps | ||
| T8 | /workspace/coverage/default/16.prim_esc_test.3112855678 | Aug 18 04:22:34 PM PDT 24 | Aug 18 04:22:34 PM PDT 24 | 5189943 ps | ||
| T11 | /workspace/coverage/default/4.prim_esc_test.2612761909 | Aug 18 04:22:03 PM PDT 24 | Aug 18 04:22:04 PM PDT 24 | 5391304 ps | ||
| T10 | /workspace/coverage/default/12.prim_esc_test.3755881981 | Aug 18 04:17:36 PM PDT 24 | Aug 18 04:17:36 PM PDT 24 | 4944141 ps | ||
| T13 | /workspace/coverage/default/8.prim_esc_test.853584411 | Aug 18 04:22:34 PM PDT 24 | Aug 18 04:22:34 PM PDT 24 | 4790196 ps | ||
| T9 | /workspace/coverage/default/15.prim_esc_test.3771501558 | Aug 18 04:21:53 PM PDT 24 | Aug 18 04:21:54 PM PDT 24 | 5221711 ps | ||
| T5 | /workspace/coverage/default/11.prim_esc_test.307958558 | Aug 18 04:17:52 PM PDT 24 | Aug 18 04:17:52 PM PDT 24 | 5338222 ps | ||
| T14 | /workspace/coverage/default/6.prim_esc_test.4033483124 | Aug 18 04:21:45 PM PDT 24 | Aug 18 04:21:45 PM PDT 24 | 4975400 ps | ||
| T12 | /workspace/coverage/default/18.prim_esc_test.545277363 | Aug 18 04:21:49 PM PDT 24 | Aug 18 04:21:50 PM PDT 24 | 5253418 ps | ||
| T15 | /workspace/coverage/default/10.prim_esc_test.2135061625 | Aug 18 04:22:24 PM PDT 24 | Aug 18 04:22:25 PM PDT 24 | 4333324 ps | ||
| T6 | /workspace/coverage/default/14.prim_esc_test.1919256971 | Aug 18 04:21:44 PM PDT 24 | Aug 18 04:21:45 PM PDT 24 | 4666162 ps | ||
| T7 | /workspace/coverage/default/1.prim_esc_test.1776204643 | Aug 18 04:19:44 PM PDT 24 | Aug 18 04:19:45 PM PDT 24 | 4875688 ps | ||
| T16 | /workspace/coverage/default/19.prim_esc_test.505022193 | Aug 18 04:21:49 PM PDT 24 | Aug 18 04:21:50 PM PDT 24 | 4428522 ps | ||
| T17 | /workspace/coverage/default/5.prim_esc_test.502470215 | Aug 18 04:17:37 PM PDT 24 | Aug 18 04:17:38 PM PDT 24 | 4631619 ps | ||
| T18 | /workspace/coverage/default/3.prim_esc_test.1764670652 | Aug 18 04:19:44 PM PDT 24 | Aug 18 04:19:45 PM PDT 24 | 5328165 ps | ||
| T19 | /workspace/coverage/default/2.prim_esc_test.2626914585 | Aug 18 04:17:10 PM PDT 24 | Aug 18 04:17:11 PM PDT 24 | 5269057 ps | ||
| T20 | /workspace/coverage/default/9.prim_esc_test.3872770608 | Aug 18 04:20:02 PM PDT 24 | Aug 18 04:20:03 PM PDT 24 | 4933361 ps |
| Test location | /workspace/coverage/default/11.prim_esc_test.307958558 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5338222 ps |
| CPU time | 0.42 seconds |
| Started | Aug 18 04:17:52 PM PDT 24 |
| Finished | Aug 18 04:17:52 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-0cf02f6a-7694-4e89-9eee-d2a5fe64065a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=307958558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.307958558 |
| Directory | /workspace/11.prim_esc_test/latest |
| Test location | /workspace/coverage/default/14.prim_esc_test.1919256971 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4666162 ps |
| CPU time | 0.37 seconds |
| Started | Aug 18 04:21:44 PM PDT 24 |
| Finished | Aug 18 04:21:45 PM PDT 24 |
| Peak memory | 146180 kb |
| Host | smart-4906a75b-0e58-492a-8166-e342f2939c7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1919256971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1919256971 |
| Directory | /workspace/14.prim_esc_test/latest |
| Test location | /workspace/coverage/default/7.prim_esc_test.1907938098 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4891482 ps |
| CPU time | 0.37 seconds |
| Started | Aug 18 04:22:30 PM PDT 24 |
| Finished | Aug 18 04:22:31 PM PDT 24 |
| Peak memory | 147168 kb |
| Host | smart-7ea3c49d-e0ae-45cc-8aa6-b82702faaae1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1907938098 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1907938098 |
| Directory | /workspace/7.prim_esc_test/latest |
| Test location | /workspace/coverage/default/10.prim_esc_test.2135061625 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4333324 ps |
| CPU time | 0.42 seconds |
| Started | Aug 18 04:22:24 PM PDT 24 |
| Finished | Aug 18 04:22:25 PM PDT 24 |
| Peak memory | 146256 kb |
| Host | smart-9b618e14-d040-4902-95c5-f56ca882b686 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2135061625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2135061625 |
| Directory | /workspace/10.prim_esc_test/latest |
| Test location | /workspace/coverage/default/13.prim_esc_test.4085059865 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5069767 ps |
| CPU time | 0.39 seconds |
| Started | Aug 18 04:21:45 PM PDT 24 |
| Finished | Aug 18 04:21:46 PM PDT 24 |
| Peak memory | 146328 kb |
| Host | smart-b5b75812-21a2-497f-8fbb-f440ad80affd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4085059865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4085059865 |
| Directory | /workspace/13.prim_esc_test/latest |
| Test location | /workspace/coverage/default/0.prim_esc_test.2314247441 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4490546 ps |
| CPU time | 0.39 seconds |
| Started | Aug 18 04:17:12 PM PDT 24 |
| Finished | Aug 18 04:17:12 PM PDT 24 |
| Peak memory | 147140 kb |
| Host | smart-97d447d9-448d-4f98-97fc-84b8602727a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314247441 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2314247441 |
| Directory | /workspace/0.prim_esc_test/latest |
| Test location | /workspace/coverage/default/1.prim_esc_test.1776204643 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4875688 ps |
| CPU time | 0.44 seconds |
| Started | Aug 18 04:19:44 PM PDT 24 |
| Finished | Aug 18 04:19:45 PM PDT 24 |
| Peak memory | 145352 kb |
| Host | smart-35fe20e1-e5fd-4bf8-98b7-a7107ec18dec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1776204643 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1776204643 |
| Directory | /workspace/1.prim_esc_test/latest |
| Test location | /workspace/coverage/default/12.prim_esc_test.3755881981 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4944141 ps |
| CPU time | 0.39 seconds |
| Started | Aug 18 04:17:36 PM PDT 24 |
| Finished | Aug 18 04:17:36 PM PDT 24 |
| Peak memory | 146160 kb |
| Host | smart-926b1434-e861-4c3a-b141-883d6de0f179 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3755881981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.3755881981 |
| Directory | /workspace/12.prim_esc_test/latest |
| Test location | /workspace/coverage/default/15.prim_esc_test.3771501558 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5221711 ps |
| CPU time | 0.37 seconds |
| Started | Aug 18 04:21:53 PM PDT 24 |
| Finished | Aug 18 04:21:54 PM PDT 24 |
| Peak memory | 146112 kb |
| Host | smart-76f0a0c0-f3ed-42d7-86fb-cbeb0028d250 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771501558 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.3771501558 |
| Directory | /workspace/15.prim_esc_test/latest |
| Test location | /workspace/coverage/default/16.prim_esc_test.3112855678 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5189943 ps |
| CPU time | 0.37 seconds |
| Started | Aug 18 04:22:34 PM PDT 24 |
| Finished | Aug 18 04:22:34 PM PDT 24 |
| Peak memory | 146332 kb |
| Host | smart-5b4f887b-d85f-4516-8986-2606f4ebd5f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3112855678 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.3112855678 |
| Directory | /workspace/16.prim_esc_test/latest |
| Test location | /workspace/coverage/default/17.prim_esc_test.2222276555 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5285627 ps |
| CPU time | 0.37 seconds |
| Started | Aug 18 04:21:44 PM PDT 24 |
| Finished | Aug 18 04:21:45 PM PDT 24 |
| Peak memory | 146900 kb |
| Host | smart-38d68d33-7feb-408b-9886-bbaf1c26161a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222276555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.2222276555 |
| Directory | /workspace/17.prim_esc_test/latest |
| Test location | /workspace/coverage/default/18.prim_esc_test.545277363 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5253418 ps |
| CPU time | 0.42 seconds |
| Started | Aug 18 04:21:49 PM PDT 24 |
| Finished | Aug 18 04:21:50 PM PDT 24 |
| Peak memory | 146348 kb |
| Host | smart-9ad98b42-a2b1-4b49-b307-2dda61b403e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=545277363 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.545277363 |
| Directory | /workspace/18.prim_esc_test/latest |
| Test location | /workspace/coverage/default/19.prim_esc_test.505022193 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4428522 ps |
| CPU time | 0.4 seconds |
| Started | Aug 18 04:21:49 PM PDT 24 |
| Finished | Aug 18 04:21:50 PM PDT 24 |
| Peak memory | 146224 kb |
| Host | smart-4e831038-ab7f-4f77-b716-572e4f664cd9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=505022193 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.505022193 |
| Directory | /workspace/19.prim_esc_test/latest |
| Test location | /workspace/coverage/default/2.prim_esc_test.2626914585 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5269057 ps |
| CPU time | 0.43 seconds |
| Started | Aug 18 04:17:10 PM PDT 24 |
| Finished | Aug 18 04:17:11 PM PDT 24 |
| Peak memory | 146388 kb |
| Host | smart-322b991b-dffe-4567-85d4-39d17718ffb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2626914585 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2626914585 |
| Directory | /workspace/2.prim_esc_test/latest |
| Test location | /workspace/coverage/default/3.prim_esc_test.1764670652 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5328165 ps |
| CPU time | 0.43 seconds |
| Started | Aug 18 04:19:44 PM PDT 24 |
| Finished | Aug 18 04:19:45 PM PDT 24 |
| Peak memory | 144096 kb |
| Host | smart-818e6385-3634-4cc5-afe9-91e8eaff6a21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1764670652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1764670652 |
| Directory | /workspace/3.prim_esc_test/latest |
| Test location | /workspace/coverage/default/4.prim_esc_test.2612761909 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5391304 ps |
| CPU time | 0.38 seconds |
| Started | Aug 18 04:22:03 PM PDT 24 |
| Finished | Aug 18 04:22:04 PM PDT 24 |
| Peak memory | 146316 kb |
| Host | smart-6ddd2557-759c-4113-92d4-3d65d2dc8f7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2612761909 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2612761909 |
| Directory | /workspace/4.prim_esc_test/latest |
| Test location | /workspace/coverage/default/5.prim_esc_test.502470215 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4631619 ps |
| CPU time | 0.39 seconds |
| Started | Aug 18 04:17:37 PM PDT 24 |
| Finished | Aug 18 04:17:38 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-608cf62c-e3fa-4132-a217-e0d70cd30894 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=502470215 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.502470215 |
| Directory | /workspace/5.prim_esc_test/latest |
| Test location | /workspace/coverage/default/6.prim_esc_test.4033483124 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4975400 ps |
| CPU time | 0.42 seconds |
| Started | Aug 18 04:21:45 PM PDT 24 |
| Finished | Aug 18 04:21:45 PM PDT 24 |
| Peak memory | 146140 kb |
| Host | smart-2d5714c4-3828-4120-978d-ee12bb336e7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033483124 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4033483124 |
| Directory | /workspace/6.prim_esc_test/latest |
| Test location | /workspace/coverage/default/8.prim_esc_test.853584411 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4790196 ps |
| CPU time | 0.37 seconds |
| Started | Aug 18 04:22:34 PM PDT 24 |
| Finished | Aug 18 04:22:34 PM PDT 24 |
| Peak memory | 146328 kb |
| Host | smart-c07cf52c-ca0f-4026-a131-ffafb457d14d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=853584411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.853584411 |
| Directory | /workspace/8.prim_esc_test/latest |
| Test location | /workspace/coverage/default/9.prim_esc_test.3872770608 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4933361 ps |
| CPU time | 0.4 seconds |
| Started | Aug 18 04:20:02 PM PDT 24 |
| Finished | Aug 18 04:20:03 PM PDT 24 |
| Peak memory | 146296 kb |
| Host | smart-03cf38d3-5913-4fdf-9bd6-313a4a71e01a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872770608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.3872770608 |
| Directory | /workspace/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |