Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.29 95.41 87.80 100.00 96.43 88.89 85.19


Total tests in report: 20
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
87.33 87.33 92.66 92.66 85.37 85.37 100.00 100.00 78.57 78.57 82.22 82.22 85.19 85.19 /workspace/coverage/default/18.prim_esc_test.1697665604
90.05 2.72 93.58 0.92 87.80 2.44 100.00 0.00 89.29 10.71 84.44 2.22 85.19 0.00 /workspace/coverage/default/6.prim_esc_test.4133223313
91.17 1.12 94.50 0.92 87.80 0.00 100.00 0.00 92.86 3.57 86.67 2.22 85.19 0.00 /workspace/coverage/default/0.prim_esc_test.663383728
92.29 1.12 95.41 0.92 87.80 0.00 100.00 0.00 96.43 3.57 88.89 2.22 85.19 0.00 /workspace/coverage/default/8.prim_esc_test.368673466

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.prim_esc_test.1976893161
/workspace/coverage/default/10.prim_esc_test.2353986977
/workspace/coverage/default/11.prim_esc_test.2679160483
/workspace/coverage/default/12.prim_esc_test.559580070
/workspace/coverage/default/13.prim_esc_test.4234059019
/workspace/coverage/default/14.prim_esc_test.3035011310
/workspace/coverage/default/15.prim_esc_test.2728655253
/workspace/coverage/default/16.prim_esc_test.4013307517
/workspace/coverage/default/17.prim_esc_test.1337764608
/workspace/coverage/default/19.prim_esc_test.2453740461
/workspace/coverage/default/2.prim_esc_test.351853823
/workspace/coverage/default/3.prim_esc_test.1791656702
/workspace/coverage/default/4.prim_esc_test.950182344
/workspace/coverage/default/5.prim_esc_test.495908082
/workspace/coverage/default/7.prim_esc_test.946640302
/workspace/coverage/default/9.prim_esc_test.566974955



Total test records in report: 20
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/18.prim_esc_test.1697665604 Aug 19 04:20:13 PM PDT 24 Aug 19 04:20:14 PM PDT 24 4953781 ps
T2 /workspace/coverage/default/0.prim_esc_test.663383728 Aug 19 04:19:15 PM PDT 24 Aug 19 04:19:16 PM PDT 24 5018361 ps
T3 /workspace/coverage/default/16.prim_esc_test.4013307517 Aug 19 04:23:58 PM PDT 24 Aug 19 04:23:58 PM PDT 24 4302696 ps
T7 /workspace/coverage/default/12.prim_esc_test.559580070 Aug 19 04:22:44 PM PDT 24 Aug 19 04:22:44 PM PDT 24 5050758 ps
T13 /workspace/coverage/default/17.prim_esc_test.1337764608 Aug 19 04:20:13 PM PDT 24 Aug 19 04:20:14 PM PDT 24 4917379 ps
T5 /workspace/coverage/default/4.prim_esc_test.950182344 Aug 19 04:18:20 PM PDT 24 Aug 19 04:18:20 PM PDT 24 5007513 ps
T4 /workspace/coverage/default/5.prim_esc_test.495908082 Aug 19 04:21:08 PM PDT 24 Aug 19 04:21:08 PM PDT 24 5253985 ps
T9 /workspace/coverage/default/13.prim_esc_test.4234059019 Aug 19 04:22:43 PM PDT 24 Aug 19 04:22:44 PM PDT 24 5295146 ps
T14 /workspace/coverage/default/2.prim_esc_test.351853823 Aug 19 04:19:29 PM PDT 24 Aug 19 04:19:30 PM PDT 24 4576387 ps
T12 /workspace/coverage/default/15.prim_esc_test.2728655253 Aug 19 04:23:56 PM PDT 24 Aug 19 04:23:57 PM PDT 24 4933664 ps
T8 /workspace/coverage/default/19.prim_esc_test.2453740461 Aug 19 04:20:00 PM PDT 24 Aug 19 04:20:01 PM PDT 24 4760035 ps
T16 /workspace/coverage/default/10.prim_esc_test.2353986977 Aug 19 04:20:40 PM PDT 24 Aug 19 04:20:40 PM PDT 24 5028341 ps
T11 /workspace/coverage/default/7.prim_esc_test.946640302 Aug 19 04:19:30 PM PDT 24 Aug 19 04:19:31 PM PDT 24 5213910 ps
T10 /workspace/coverage/default/6.prim_esc_test.4133223313 Aug 19 04:18:13 PM PDT 24 Aug 19 04:18:14 PM PDT 24 5209577 ps
T6 /workspace/coverage/default/8.prim_esc_test.368673466 Aug 19 04:19:30 PM PDT 24 Aug 19 04:19:30 PM PDT 24 4519119 ps
T17 /workspace/coverage/default/9.prim_esc_test.566974955 Aug 19 04:19:16 PM PDT 24 Aug 19 04:19:16 PM PDT 24 5275579 ps
T18 /workspace/coverage/default/3.prim_esc_test.1791656702 Aug 19 04:18:13 PM PDT 24 Aug 19 04:18:13 PM PDT 24 4531580 ps
T15 /workspace/coverage/default/1.prim_esc_test.1976893161 Aug 19 04:19:16 PM PDT 24 Aug 19 04:19:16 PM PDT 24 4967806 ps
T19 /workspace/coverage/default/11.prim_esc_test.2679160483 Aug 19 04:19:15 PM PDT 24 Aug 19 04:19:16 PM PDT 24 4915494 ps
T20 /workspace/coverage/default/14.prim_esc_test.3035011310 Aug 19 04:19:17 PM PDT 24 Aug 19 04:19:18 PM PDT 24 4661835 ps

Test location /workspace/coverage/default/18.prim_esc_test.1697665604
Short name T1
Test name
Test status
Simulation time 4953781 ps
CPU time 0.37 seconds
Started Aug 19 04:20:13 PM PDT 24
Finished Aug 19 04:20:14 PM PDT 24
Peak memory 146304 kb
Host smart-a6dc1847-e1d5-41f7-b54d-b720b3b71e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697665604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1697665604
Directory /workspace/18.prim_esc_test/latest

Test location /workspace/coverage/default/6.prim_esc_test.4133223313
Short name T10
Test name
Test status
Simulation time 5209577 ps
CPU time 0.38 seconds
Started Aug 19 04:18:13 PM PDT 24
Finished Aug 19 04:18:14 PM PDT 24
Peak memory 146448 kb
Host smart-ed43b827-702b-420b-8b50-1cc3039cfe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133223313 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.4133223313
Directory /workspace/6.prim_esc_test/latest

Test location /workspace/coverage/default/0.prim_esc_test.663383728
Short name T2
Test name
Test status
Simulation time 5018361 ps
CPU time 0.41 seconds
Started Aug 19 04:19:15 PM PDT 24
Finished Aug 19 04:19:16 PM PDT 24
Peak memory 145880 kb
Host smart-7e5bffaf-40dd-42f0-8838-7132f390edc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663383728 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.663383728
Directory /workspace/0.prim_esc_test/latest

Test location /workspace/coverage/default/8.prim_esc_test.368673466
Short name T6
Test name
Test status
Simulation time 4519119 ps
CPU time 0.4 seconds
Started Aug 19 04:19:30 PM PDT 24
Finished Aug 19 04:19:30 PM PDT 24
Peak memory 146260 kb
Host smart-90bd87f3-8ca1-4f79-af6a-164217b4018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368673466 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.368673466
Directory /workspace/8.prim_esc_test/latest

Test location /workspace/coverage/default/1.prim_esc_test.1976893161
Short name T15
Test name
Test status
Simulation time 4967806 ps
CPU time 0.39 seconds
Started Aug 19 04:19:16 PM PDT 24
Finished Aug 19 04:19:16 PM PDT 24
Peak memory 144680 kb
Host smart-bd7fa742-d7d5-4c9d-96af-24b4a0d87cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976893161 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.1976893161
Directory /workspace/1.prim_esc_test/latest

Test location /workspace/coverage/default/10.prim_esc_test.2353986977
Short name T16
Test name
Test status
Simulation time 5028341 ps
CPU time 0.42 seconds
Started Aug 19 04:20:40 PM PDT 24
Finished Aug 19 04:20:40 PM PDT 24
Peak memory 146216 kb
Host smart-0704d450-3f94-4590-8122-9adfe71f27da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353986977 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2353986977
Directory /workspace/10.prim_esc_test/latest

Test location /workspace/coverage/default/11.prim_esc_test.2679160483
Short name T19
Test name
Test status
Simulation time 4915494 ps
CPU time 0.36 seconds
Started Aug 19 04:19:15 PM PDT 24
Finished Aug 19 04:19:16 PM PDT 24
Peak memory 147228 kb
Host smart-aabefb86-636f-4053-9c2a-26bb0d3023db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679160483 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.2679160483
Directory /workspace/11.prim_esc_test/latest

Test location /workspace/coverage/default/12.prim_esc_test.559580070
Short name T7
Test name
Test status
Simulation time 5050758 ps
CPU time 0.36 seconds
Started Aug 19 04:22:44 PM PDT 24
Finished Aug 19 04:22:44 PM PDT 24
Peak memory 146884 kb
Host smart-0f475905-1978-46c8-bc97-1d6c12bbfe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559580070 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.559580070
Directory /workspace/12.prim_esc_test/latest

Test location /workspace/coverage/default/13.prim_esc_test.4234059019
Short name T9
Test name
Test status
Simulation time 5295146 ps
CPU time 0.45 seconds
Started Aug 19 04:22:43 PM PDT 24
Finished Aug 19 04:22:44 PM PDT 24
Peak memory 145348 kb
Host smart-b7fa1950-d196-4ec4-8ea4-5894a7584acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234059019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.4234059019
Directory /workspace/13.prim_esc_test/latest

Test location /workspace/coverage/default/14.prim_esc_test.3035011310
Short name T20
Test name
Test status
Simulation time 4661835 ps
CPU time 0.37 seconds
Started Aug 19 04:19:17 PM PDT 24
Finished Aug 19 04:19:18 PM PDT 24
Peak memory 147324 kb
Host smart-aaec83ba-a177-46d8-9ea1-bc3d93946aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035011310 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.3035011310
Directory /workspace/14.prim_esc_test/latest

Test location /workspace/coverage/default/15.prim_esc_test.2728655253
Short name T12
Test name
Test status
Simulation time 4933664 ps
CPU time 0.42 seconds
Started Aug 19 04:23:56 PM PDT 24
Finished Aug 19 04:23:57 PM PDT 24
Peak memory 146668 kb
Host smart-48f59ee5-d601-494c-88b1-430dc7acee97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728655253 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.2728655253
Directory /workspace/15.prim_esc_test/latest

Test location /workspace/coverage/default/16.prim_esc_test.4013307517
Short name T3
Test name
Test status
Simulation time 4302696 ps
CPU time 0.36 seconds
Started Aug 19 04:23:58 PM PDT 24
Finished Aug 19 04:23:58 PM PDT 24
Peak memory 146152 kb
Host smart-878d0c8b-d3f3-444c-acd0-f93865fc6a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013307517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.4013307517
Directory /workspace/16.prim_esc_test/latest

Test location /workspace/coverage/default/17.prim_esc_test.1337764608
Short name T13
Test name
Test status
Simulation time 4917379 ps
CPU time 0.38 seconds
Started Aug 19 04:20:13 PM PDT 24
Finished Aug 19 04:20:14 PM PDT 24
Peak memory 146304 kb
Host smart-c7d8e12c-8895-4048-91bc-766b2096caef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337764608 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1337764608
Directory /workspace/17.prim_esc_test/latest

Test location /workspace/coverage/default/19.prim_esc_test.2453740461
Short name T8
Test name
Test status
Simulation time 4760035 ps
CPU time 0.37 seconds
Started Aug 19 04:20:00 PM PDT 24
Finished Aug 19 04:20:01 PM PDT 24
Peak memory 146292 kb
Host smart-39699917-dc12-4421-9529-4e459572f6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453740461 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.2453740461
Directory /workspace/19.prim_esc_test/latest

Test location /workspace/coverage/default/2.prim_esc_test.351853823
Short name T14
Test name
Test status
Simulation time 4576387 ps
CPU time 0.41 seconds
Started Aug 19 04:19:29 PM PDT 24
Finished Aug 19 04:19:30 PM PDT 24
Peak memory 146296 kb
Host smart-0fd07768-8157-4772-976b-4f5d60675533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351853823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.351853823
Directory /workspace/2.prim_esc_test/latest

Test location /workspace/coverage/default/3.prim_esc_test.1791656702
Short name T18
Test name
Test status
Simulation time 4531580 ps
CPU time 0.37 seconds
Started Aug 19 04:18:13 PM PDT 24
Finished Aug 19 04:18:13 PM PDT 24
Peak memory 146400 kb
Host smart-12a854d6-1174-4217-8817-401e12c3a584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791656702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.1791656702
Directory /workspace/3.prim_esc_test/latest

Test location /workspace/coverage/default/4.prim_esc_test.950182344
Short name T5
Test name
Test status
Simulation time 5007513 ps
CPU time 0.4 seconds
Started Aug 19 04:18:20 PM PDT 24
Finished Aug 19 04:18:20 PM PDT 24
Peak memory 146484 kb
Host smart-b25288c2-8b6d-4eb7-a386-7a3b89adaded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950182344 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.950182344
Directory /workspace/4.prim_esc_test/latest

Test location /workspace/coverage/default/5.prim_esc_test.495908082
Short name T4
Test name
Test status
Simulation time 5253985 ps
CPU time 0.38 seconds
Started Aug 19 04:21:08 PM PDT 24
Finished Aug 19 04:21:08 PM PDT 24
Peak memory 146236 kb
Host smart-aa0eca6c-8eb4-4774-aff9-8c46bd182b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495908082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.495908082
Directory /workspace/5.prim_esc_test/latest

Test location /workspace/coverage/default/7.prim_esc_test.946640302
Short name T11
Test name
Test status
Simulation time 5213910 ps
CPU time 0.39 seconds
Started Aug 19 04:19:30 PM PDT 24
Finished Aug 19 04:19:31 PM PDT 24
Peak memory 146260 kb
Host smart-fec5a92e-eab6-45b8-bfd9-de86ef02ceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946640302 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.946640302
Directory /workspace/7.prim_esc_test/latest

Test location /workspace/coverage/default/9.prim_esc_test.566974955
Short name T17
Test name
Test status
Simulation time 5275579 ps
CPU time 0.4 seconds
Started Aug 19 04:19:16 PM PDT 24
Finished Aug 19 04:19:16 PM PDT 24
Peak memory 145864 kb
Host smart-e63f39ac-6d66-4a76-b7a4-6e1aeb54d8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566974955 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.566974955
Directory /workspace/9.prim_esc_test/latest
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