| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.74 | 87.74 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 78.57 | 78.57 | 82.22 | 82.22 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3496664088 |
| 89.45 | 1.71 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 7.14 | 84.44 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1161790991 |
| 90.57 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.54333001 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.267932320 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.3535414513 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.2891036378 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1407115489 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2215261371 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.589946325 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3185049327 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.576076082 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.3507363772 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3829112006 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.273811382 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1638825205 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.1380321838 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2626352219 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2066530874 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.4021239971 |
| /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.680891600 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.2891036378 | Aug 23 09:14:09 PM UTC 24 | Aug 23 09:14:10 PM UTC 24 | 5101336 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1638825205 | Aug 23 09:14:10 PM UTC 24 | Aug 23 09:14:12 PM UTC 24 | 5290226 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.1380321838 | Aug 23 09:14:10 PM UTC 24 | Aug 23 09:14:12 PM UTC 24 | 4768835 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1407115489 | Aug 23 09:14:10 PM UTC 24 | Aug 23 09:14:12 PM UTC 24 | 5612391 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2626352219 | Aug 23 09:14:10 PM UTC 24 | Aug 23 09:14:12 PM UTC 24 | 4588792 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.267932320 | Aug 23 09:14:10 PM UTC 24 | Aug 23 09:14:12 PM UTC 24 | 4888975 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2066530874 | Aug 23 09:14:12 PM UTC 24 | Aug 23 09:14:13 PM UTC 24 | 4745878 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.4021239971 | Aug 23 09:14:13 PM UTC 24 | Aug 23 09:14:15 PM UTC 24 | 4567451 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3496664088 | Aug 23 09:14:13 PM UTC 24 | Aug 23 09:14:15 PM UTC 24 | 4962345 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2215261371 | Aug 23 09:14:13 PM UTC 24 | Aug 23 09:14:15 PM UTC 24 | 4769278 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.680891600 | Aug 23 09:14:13 PM UTC 24 | Aug 23 09:14:15 PM UTC 24 | 5543356 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.589946325 | Aug 23 09:14:13 PM UTC 24 | Aug 23 09:14:15 PM UTC 24 | 5167289 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.3535414513 | Aug 23 09:14:13 PM UTC 24 | Aug 23 09:14:15 PM UTC 24 | 4432302 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1161790991 | Aug 23 09:14:13 PM UTC 24 | Aug 23 09:14:15 PM UTC 24 | 5203540 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.54333001 | Aug 23 09:14:13 PM UTC 24 | Aug 23 09:14:15 PM UTC 24 | 4644520 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.576076082 | Aug 23 09:14:13 PM UTC 24 | Aug 23 09:14:15 PM UTC 24 | 4720039 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3185049327 | Aug 23 09:14:13 PM UTC 24 | Aug 23 09:14:15 PM UTC 24 | 5387737 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.3507363772 | Aug 23 09:14:14 PM UTC 24 | Aug 23 09:14:16 PM UTC 24 | 5189800 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.273811382 | Aug 23 09:14:17 PM UTC 24 | Aug 23 09:14:18 PM UTC 24 | 4878326 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3829112006 | Aug 23 09:14:16 PM UTC 24 | Aug 23 09:14:18 PM UTC 24 | 4999087 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3496664088 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4962345 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 09:14:13 PM UTC 24 |
| Finished | Aug 23 09:14:15 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496664088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.prim_esc_test.3496664088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/9.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1161790991 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5203540 ps |
| CPU time | 0.36 seconds |
| Started | Aug 23 09:14:13 PM UTC 24 |
| Finished | Aug 23 09:14:15 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161790991 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.prim_esc_test.1161790991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.54333001 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4644520 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 09:14:13 PM UTC 24 |
| Finished | Aug 23 09:14:15 PM UTC 24 |
| Peak memory | 156092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54333001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.54333001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.267932320 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4888975 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 09:14:10 PM UTC 24 |
| Finished | Aug 23 09:14:12 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267932320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 5.prim_esc_test.267932320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.3535414513 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4432302 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 09:14:13 PM UTC 24 |
| Finished | Aug 23 09:14:15 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535414513 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.prim_esc_test.3535414513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.2891036378 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5101336 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 09:14:09 PM UTC 24 |
| Finished | Aug 23 09:14:10 PM UTC 24 |
| Peak memory | 156144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891036378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.2891036378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1407115489 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5612391 ps |
| CPU time | 0.37 seconds |
| Started | Aug 23 09:14:10 PM UTC 24 |
| Finished | Aug 23 09:14:12 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407115489 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.prim_esc_test.1407115489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2215261371 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4769278 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 09:14:13 PM UTC 24 |
| Finished | Aug 23 09:14:15 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215261371 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.prim_esc_test.2215261371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.589946325 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5167289 ps |
| CPU time | 0.32 seconds |
| Started | Aug 23 09:14:13 PM UTC 24 |
| Finished | Aug 23 09:14:15 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589946325 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 12.prim_esc_test.589946325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3185049327 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5387737 ps |
| CPU time | 0.34 seconds |
| Started | Aug 23 09:14:13 PM UTC 24 |
| Finished | Aug 23 09:14:15 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185049327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.prim_esc_test.3185049327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.576076082 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4720039 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 09:14:13 PM UTC 24 |
| Finished | Aug 23 09:14:15 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576076082 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 16.prim_esc_test.576076082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.3507363772 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5189800 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 09:14:14 PM UTC 24 |
| Finished | Aug 23 09:14:16 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507363772 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.prim_esc_test.3507363772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3829112006 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4999087 ps |
| CPU time | 0.41 seconds |
| Started | Aug 23 09:14:16 PM UTC 24 |
| Finished | Aug 23 09:14:18 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829112006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.3829112006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.273811382 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4878326 ps |
| CPU time | 0.36 seconds |
| Started | Aug 23 09:14:17 PM UTC 24 |
| Finished | Aug 23 09:14:18 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273811382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 19.prim_esc_test.273811382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1638825205 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5290226 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 09:14:10 PM UTC 24 |
| Finished | Aug 23 09:14:12 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638825205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.prim_esc_test.1638825205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.1380321838 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4768835 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 09:14:10 PM UTC 24 |
| Finished | Aug 23 09:14:12 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380321838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.prim_esc_test.1380321838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2626352219 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4588792 ps |
| CPU time | 0.35 seconds |
| Started | Aug 23 09:14:10 PM UTC 24 |
| Finished | Aug 23 09:14:12 PM UTC 24 |
| Peak memory | 155240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626352219 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.prim_esc_test.2626352219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2066530874 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4745878 ps |
| CPU time | 0.36 seconds |
| Started | Aug 23 09:14:12 PM UTC 24 |
| Finished | Aug 23 09:14:13 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066530874 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.prim_esc_test.2066530874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.4021239971 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4567451 ps |
| CPU time | 0.33 seconds |
| Started | Aug 23 09:14:13 PM UTC 24 |
| Finished | Aug 23 09:14:15 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021239971 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.prim_esc_test.4021239971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.680891600 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5543356 ps |
| CPU time | 0.38 seconds |
| Started | Aug 23 09:14:13 PM UTC 24 |
| Finished | Aug 23 09:14:15 PM UTC 24 |
| Peak memory | 156052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680891600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 8.prim_esc_test.680891600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/prim_esc-sim-vcs/8.prim_esc_test/latest |
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