| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.06 | 86.06 | 90.83 | 90.83 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 80.00 | 80.00 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.2579269236 |
| 88.86 | 2.80 | 93.58 | 2.75 | 87.80 | 2.44 | 100.00 | 0.00 | 82.14 | 7.14 | 84.44 | 4.44 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1627259903 |
| 90.57 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.895750138 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.3585696895 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.3654039085 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.2389614010 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.1794119817 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3215294365 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.1259919880 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.174889320 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.681673105 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.1079349880 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2982981663 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.2786442490 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1817421176 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.2747349015 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.797062191 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.1484843149 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.2955103001 |
| /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3681314468 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.2389614010 | Aug 24 09:34:38 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 5063892 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.2579269236 | Aug 24 09:34:37 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 4999350 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1817421176 | Aug 24 09:34:38 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 4824666 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.797062191 | Aug 24 09:34:38 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 4493701 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.2747349015 | Aug 24 09:34:38 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 5036988 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.895750138 | Aug 24 09:34:38 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 5550507 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.2955103001 | Aug 24 09:34:38 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 4666077 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.1484843149 | Aug 24 09:34:38 PM UTC 24 | Aug 24 09:34:39 PM UTC 24 | 5877379 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.3585696895 | Aug 24 09:34:38 PM UTC 24 | Aug 24 09:34:40 PM UTC 24 | 5140029 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3681314468 | Aug 24 09:34:38 PM UTC 24 | Aug 24 09:34:40 PM UTC 24 | 4791238 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1627259903 | Aug 24 09:34:38 PM UTC 24 | Aug 24 09:34:40 PM UTC 24 | 4812604 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.3654039085 | Aug 24 09:34:38 PM UTC 24 | Aug 24 09:34:40 PM UTC 24 | 5154474 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.1794119817 | Aug 24 09:34:39 PM UTC 24 | Aug 24 09:34:41 PM UTC 24 | 5414401 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3215294365 | Aug 24 09:34:39 PM UTC 24 | Aug 24 09:34:41 PM UTC 24 | 4791673 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.1259919880 | Aug 24 09:34:39 PM UTC 24 | Aug 24 09:34:41 PM UTC 24 | 5161838 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.174889320 | Aug 24 09:34:40 PM UTC 24 | Aug 24 09:34:41 PM UTC 24 | 5119310 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.681673105 | Aug 24 09:34:40 PM UTC 24 | Aug 24 09:34:41 PM UTC 24 | 4731853 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.1079349880 | Aug 24 09:34:40 PM UTC 24 | Aug 24 09:34:41 PM UTC 24 | 4661464 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2982981663 | Aug 24 09:34:40 PM UTC 24 | Aug 24 09:34:41 PM UTC 24 | 5020152 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.2786442490 | Aug 24 09:34:40 PM UTC 24 | Aug 24 09:34:41 PM UTC 24 | 5304103 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.2579269236 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4999350 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:37 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579269236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.2579269236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1627259903 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4812604 ps |
| CPU time | 0.55 seconds |
| Started | Aug 24 09:34:38 PM UTC 24 |
| Finished | Aug 24 09:34:40 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627259903 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.prim_esc_test.1627259903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.895750138 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5550507 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:38 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895750138 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 5.prim_esc_test.895750138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.3585696895 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5140029 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:38 PM UTC 24 |
| Finished | Aug 24 09:34:40 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585696895 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.prim_esc_test.3585696895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.3654039085 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5154474 ps |
| CPU time | 0.55 seconds |
| Started | Aug 24 09:34:38 PM UTC 24 |
| Finished | Aug 24 09:34:40 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654039085 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.prim_esc_test.3654039085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.2389614010 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5063892 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:38 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 156144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389614010 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.prim_esc_test.2389614010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.1794119817 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 5414401 ps |
| CPU time | 0.55 seconds |
| Started | Aug 24 09:34:39 PM UTC 24 |
| Finished | Aug 24 09:34:41 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794119817 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.prim_esc_test.1794119817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3215294365 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4791673 ps |
| CPU time | 0.55 seconds |
| Started | Aug 24 09:34:39 PM UTC 24 |
| Finished | Aug 24 09:34:41 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215294365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.prim_esc_test.3215294365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.1259919880 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5161838 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:39 PM UTC 24 |
| Finished | Aug 24 09:34:41 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259919880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.prim_esc_test.1259919880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.174889320 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5119310 ps |
| CPU time | 0.55 seconds |
| Started | Aug 24 09:34:40 PM UTC 24 |
| Finished | Aug 24 09:34:41 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174889320 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 15.prim_esc_test.174889320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.681673105 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4731853 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:40 PM UTC 24 |
| Finished | Aug 24 09:34:41 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681673105 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 16.prim_esc_test.681673105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.1079349880 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4661464 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:40 PM UTC 24 |
| Finished | Aug 24 09:34:41 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079349880 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.prim_esc_test.1079349880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2982981663 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5020152 ps |
| CPU time | 0.55 seconds |
| Started | Aug 24 09:34:40 PM UTC 24 |
| Finished | Aug 24 09:34:41 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982981663 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.2982981663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.2786442490 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5304103 ps |
| CPU time | 0.55 seconds |
| Started | Aug 24 09:34:40 PM UTC 24 |
| Finished | Aug 24 09:34:41 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786442490 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.prim_esc_test.2786442490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1817421176 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4824666 ps |
| CPU time | 0.55 seconds |
| Started | Aug 24 09:34:38 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817421176 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.prim_esc_test.1817421176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.2747349015 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5036988 ps |
| CPU time | 0.57 seconds |
| Started | Aug 24 09:34:38 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747349015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.prim_esc_test.2747349015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.797062191 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4493701 ps |
| CPU time | 0.55 seconds |
| Started | Aug 24 09:34:38 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797062191 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 4.prim_esc_test.797062191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.1484843149 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5877379 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:38 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484843149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.prim_esc_test.1484843149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.2955103001 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4666077 ps |
| CPU time | 0.54 seconds |
| Started | Aug 24 09:34:38 PM UTC 24 |
| Finished | Aug 24 09:34:39 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955103001 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.prim_esc_test.2955103001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3681314468 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4791238 ps |
| CPU time | 0.56 seconds |
| Started | Aug 24 09:34:38 PM UTC 24 |
| Finished | Aug 24 09:34:40 PM UTC 24 |
| Peak memory | 155976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681314468 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.prim_esc_test.3681314468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_24/prim_esc-sim-vcs/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |