| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.151791702 |
| 89.45 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1937369154 |
| 91.17 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.291621923 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1198349168 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3216655935 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.761137346 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.3007502076 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.2358204467 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.575145096 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.3587205702 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.105508255 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2337500508 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3705060475 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.4236147590 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.2138776356 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3884301749 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.3494800281 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.1754660970 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.1981874373 |
| /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.584813781 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3216655935 | Aug 27 12:03:22 AM UTC 24 | Aug 27 12:03:24 AM UTC 24 | 3942762 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.2138776356 | Aug 27 12:03:23 AM UTC 24 | Aug 27 12:03:24 AM UTC 24 | 4751906 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1198349168 | Aug 27 12:03:22 AM UTC 24 | Aug 27 12:03:24 AM UTC 24 | 4629854 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1937369154 | Aug 27 12:03:23 AM UTC 24 | Aug 27 12:03:24 AM UTC 24 | 4327752 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.3494800281 | Aug 27 12:03:23 AM UTC 24 | Aug 27 12:03:24 AM UTC 24 | 4855764 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3884301749 | Aug 27 12:03:23 AM UTC 24 | Aug 27 12:03:24 AM UTC 24 | 5027509 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.151791702 | Aug 27 12:03:23 AM UTC 24 | Aug 27 12:03:24 AM UTC 24 | 4761277 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.1754660970 | Aug 27 12:03:23 AM UTC 24 | Aug 27 12:03:24 AM UTC 24 | 4826902 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.1981874373 | Aug 27 12:03:23 AM UTC 24 | Aug 27 12:03:24 AM UTC 24 | 5291327 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.291621923 | Aug 27 12:03:23 AM UTC 24 | Aug 27 12:03:24 AM UTC 24 | 4736988 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.584813781 | Aug 27 12:03:23 AM UTC 24 | Aug 27 12:03:24 AM UTC 24 | 5168887 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.761137346 | Aug 27 12:03:23 AM UTC 24 | Aug 27 12:03:25 AM UTC 24 | 5066288 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.3007502076 | Aug 27 12:03:24 AM UTC 24 | Aug 27 12:03:25 AM UTC 24 | 4772724 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.2358204467 | Aug 27 12:03:24 AM UTC 24 | Aug 27 12:03:25 AM UTC 24 | 4863167 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.575145096 | Aug 27 12:03:24 AM UTC 24 | Aug 27 12:03:26 AM UTC 24 | 4963905 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.3587205702 | Aug 27 12:03:24 AM UTC 24 | Aug 27 12:03:26 AM UTC 24 | 5175538 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.105508255 | Aug 27 12:03:24 AM UTC 24 | Aug 27 12:03:26 AM UTC 24 | 4784250 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2337500508 | Aug 27 12:03:24 AM UTC 24 | Aug 27 12:03:26 AM UTC 24 | 5278345 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.4236147590 | Aug 27 12:03:24 AM UTC 24 | Aug 27 12:03:26 AM UTC 24 | 5375051 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3705060475 | Aug 27 12:03:24 AM UTC 24 | Aug 27 12:03:26 AM UTC 24 | 4697501 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.151791702 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4761277 ps |
| CPU time | 0.39 seconds |
| Started | Aug 27 12:03:23 AM UTC 24 |
| Finished | Aug 27 12:03:24 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151791702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 8.prim_esc_test.151791702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1937369154 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4327752 ps |
| CPU time | 0.5 seconds |
| Started | Aug 27 12:03:23 AM UTC 24 |
| Finished | Aug 27 12:03:24 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937369154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.prim_esc_test.1937369154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.291621923 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4736988 ps |
| CPU time | 0.46 seconds |
| Started | Aug 27 12:03:23 AM UTC 24 |
| Finished | Aug 27 12:03:24 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291621923 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 10.prim_esc_test.291621923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1198349168 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4629854 ps |
| CPU time | 0.51 seconds |
| Started | Aug 27 12:03:22 AM UTC 24 |
| Finished | Aug 27 12:03:24 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198349168 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.prim_esc_test.1198349168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3216655935 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3942762 ps |
| CPU time | 0.53 seconds |
| Started | Aug 27 12:03:22 AM UTC 24 |
| Finished | Aug 27 12:03:24 AM UTC 24 |
| Peak memory | 156152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216655935 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.3216655935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.761137346 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5066288 ps |
| CPU time | 0.47 seconds |
| Started | Aug 27 12:03:23 AM UTC 24 |
| Finished | Aug 27 12:03:25 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761137346 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 11.prim_esc_test.761137346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.3007502076 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4772724 ps |
| CPU time | 0.42 seconds |
| Started | Aug 27 12:03:24 AM UTC 24 |
| Finished | Aug 27 12:03:25 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007502076 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.prim_esc_test.3007502076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.2358204467 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4863167 ps |
| CPU time | 0.42 seconds |
| Started | Aug 27 12:03:24 AM UTC 24 |
| Finished | Aug 27 12:03:25 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358204467 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.prim_esc_test.2358204467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.575145096 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4963905 ps |
| CPU time | 0.41 seconds |
| Started | Aug 27 12:03:24 AM UTC 24 |
| Finished | Aug 27 12:03:26 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575145096 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 14.prim_esc_test.575145096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.3587205702 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5175538 ps |
| CPU time | 0.45 seconds |
| Started | Aug 27 12:03:24 AM UTC 24 |
| Finished | Aug 27 12:03:26 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587205702 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.prim_esc_test.3587205702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.105508255 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4784250 ps |
| CPU time | 0.49 seconds |
| Started | Aug 27 12:03:24 AM UTC 24 |
| Finished | Aug 27 12:03:26 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105508255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 16.prim_esc_test.105508255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2337500508 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5278345 ps |
| CPU time | 0.44 seconds |
| Started | Aug 27 12:03:24 AM UTC 24 |
| Finished | Aug 27 12:03:26 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337500508 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.prim_esc_test.2337500508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3705060475 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4697501 ps |
| CPU time | 0.52 seconds |
| Started | Aug 27 12:03:24 AM UTC 24 |
| Finished | Aug 27 12:03:26 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705060475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.3705060475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.4236147590 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 5375051 ps |
| CPU time | 0.4 seconds |
| Started | Aug 27 12:03:24 AM UTC 24 |
| Finished | Aug 27 12:03:26 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236147590 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.prim_esc_test.4236147590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.2138776356 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4751906 ps |
| CPU time | 0.43 seconds |
| Started | Aug 27 12:03:23 AM UTC 24 |
| Finished | Aug 27 12:03:24 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138776356 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.prim_esc_test.2138776356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3884301749 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5027509 ps |
| CPU time | 0.48 seconds |
| Started | Aug 27 12:03:23 AM UTC 24 |
| Finished | Aug 27 12:03:24 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884301749 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.prim_esc_test.3884301749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.3494800281 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4855764 ps |
| CPU time | 0.44 seconds |
| Started | Aug 27 12:03:23 AM UTC 24 |
| Finished | Aug 27 12:03:24 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494800281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.prim_esc_test.3494800281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.1754660970 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4826902 ps |
| CPU time | 0.52 seconds |
| Started | Aug 27 12:03:23 AM UTC 24 |
| Finished | Aug 27 12:03:24 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754660970 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.prim_esc_test.1754660970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.1981874373 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5291327 ps |
| CPU time | 0.56 seconds |
| Started | Aug 27 12:03:23 AM UTC 24 |
| Finished | Aug 27 12:03:24 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981874373 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.prim_esc_test.1981874373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.584813781 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5168887 ps |
| CPU time | 0.49 seconds |
| Started | Aug 27 12:03:23 AM UTC 24 |
| Finished | Aug 27 12:03:24 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584813781 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 9.prim_esc_test.584813781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/prim_esc-sim-vcs/9.prim_esc_test/latest |
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