| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.4293995961 |
| 89.45 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.4228675890 |
| 90.57 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3169453823 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1520848187 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.2615156419 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.653583623 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2964886210 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1607534431 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.3184974579 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.1910171521 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.1320449159 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2626401844 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.1657592498 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.398383620 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.1733547455 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2312956555 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.3668277137 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.809595255 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.994631812 |
| /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3869796396 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1520848187 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 5535429 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.4228675890 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 4891917 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.4293995961 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 4541387 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.653583623 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 4591821 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.1733547455 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 4515514 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2312956555 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 4998856 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.3668277137 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 4927669 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.994631812 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 4970996 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.809595255 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 4807929 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3869796396 | Aug 28 04:59:46 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 4330394 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1607534431 | Aug 28 04:59:47 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 5130232 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2964886210 | Aug 28 04:59:47 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 4808578 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.3184974579 | Aug 28 04:59:47 PM UTC 24 | Aug 28 04:59:48 PM UTC 24 | 4360919 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.1320449159 | Aug 28 04:59:48 PM UTC 24 | Aug 28 04:59:49 PM UTC 24 | 5329095 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3169453823 | Aug 28 04:59:48 PM UTC 24 | Aug 28 04:59:49 PM UTC 24 | 4777901 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.2615156419 | Aug 28 04:59:48 PM UTC 24 | Aug 28 04:59:49 PM UTC 24 | 5204004 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2626401844 | Aug 28 04:59:48 PM UTC 24 | Aug 28 04:59:49 PM UTC 24 | 5027440 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.1910171521 | Aug 28 04:59:48 PM UTC 24 | Aug 28 04:59:49 PM UTC 24 | 4582959 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.1657592498 | Aug 28 04:59:48 PM UTC 24 | Aug 28 04:59:49 PM UTC 24 | 4495573 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.398383620 | Aug 28 04:59:48 PM UTC 24 | Aug 28 04:59:50 PM UTC 24 | 4983634 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.4293995961 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4541387 ps |
| CPU time | 0.36 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293995961 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.prim_esc_test.4293995961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.4228675890 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4891917 ps |
| CPU time | 0.41 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228675890 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.4228675890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3169453823 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4777901 ps |
| CPU time | 0.36 seconds |
| Started | Aug 28 04:59:48 PM UTC 24 |
| Finished | Aug 28 04:59:49 PM UTC 24 |
| Peak memory | 154880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169453823 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.prim_esc_test.3169453823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.1520848187 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5535429 ps |
| CPU time | 0.37 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520848187 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.prim_esc_test.1520848187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.2615156419 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5204004 ps |
| CPU time | 0.34 seconds |
| Started | Aug 28 04:59:48 PM UTC 24 |
| Finished | Aug 28 04:59:49 PM UTC 24 |
| Peak memory | 155056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615156419 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.prim_esc_test.2615156419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.653583623 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4591821 ps |
| CPU time | 0.42 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653583623 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.prim_esc_test.653583623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2964886210 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4808578 ps |
| CPU time | 0.34 seconds |
| Started | Aug 28 04:59:47 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964886210 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.prim_esc_test.2964886210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1607534431 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5130232 ps |
| CPU time | 0.37 seconds |
| Started | Aug 28 04:59:47 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607534431 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.prim_esc_test.1607534431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.3184974579 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4360919 ps |
| CPU time | 0.34 seconds |
| Started | Aug 28 04:59:47 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184974579 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.prim_esc_test.3184974579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.1910171521 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4582959 ps |
| CPU time | 0.39 seconds |
| Started | Aug 28 04:59:48 PM UTC 24 |
| Finished | Aug 28 04:59:49 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910171521 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.prim_esc_test.1910171521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.1320449159 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5329095 ps |
| CPU time | 0.35 seconds |
| Started | Aug 28 04:59:48 PM UTC 24 |
| Finished | Aug 28 04:59:49 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320449159 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.prim_esc_test.1320449159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2626401844 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5027440 ps |
| CPU time | 0.35 seconds |
| Started | Aug 28 04:59:48 PM UTC 24 |
| Finished | Aug 28 04:59:49 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626401844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.prim_esc_test.2626401844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.1657592498 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4495573 ps |
| CPU time | 0.34 seconds |
| Started | Aug 28 04:59:48 PM UTC 24 |
| Finished | Aug 28 04:59:49 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657592498 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.1657592498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.398383620 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4983634 ps |
| CPU time | 0.36 seconds |
| Started | Aug 28 04:59:48 PM UTC 24 |
| Finished | Aug 28 04:59:50 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398383620 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 19.prim_esc_test.398383620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.1733547455 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4515514 ps |
| CPU time | 0.41 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733547455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.prim_esc_test.1733547455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2312956555 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4998856 ps |
| CPU time | 0.36 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312956555 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.prim_esc_test.2312956555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.3668277137 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4927669 ps |
| CPU time | 0.35 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668277137 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.prim_esc_test.3668277137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.809595255 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4807929 ps |
| CPU time | 0.33 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809595255 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 7.prim_esc_test.809595255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.994631812 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4970996 ps |
| CPU time | 0.34 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994631812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 8.prim_esc_test.994631812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3869796396 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4330394 ps |
| CPU time | 0.33 seconds |
| Started | Aug 28 04:59:46 PM UTC 24 |
| Finished | Aug 28 04:59:48 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869796396 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.prim_esc_test.3869796396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/prim_esc-sim-vcs/9.prim_esc_test/latest |
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