| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.33 | 87.33 | 92.66 | 92.66 | 85.37 | 85.37 | 100.00 | 100.00 | 78.57 | 78.57 | 82.22 | 82.22 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.3187711769 |
| 89.45 | 2.12 | 93.58 | 0.92 | 87.80 | 2.44 | 100.00 | 0.00 | 85.71 | 7.14 | 84.44 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3840242130 |
| 90.57 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.52970434 |
| 91.69 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.3586743211 |
| 92.29 | 0.60 | 95.41 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 0.00 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2411734087 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.2708648343 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1513993352 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1028083814 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.249778664 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3771539475 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.3263249214 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3385605493 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.691035065 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.2594593549 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3513301211 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.1483382951 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.1091114104 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.882484632 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.3883253382 |
| /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2819385222 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.2708648343 | Sep 01 03:33:09 AM UTC 24 | Sep 01 03:33:11 AM UTC 24 | 4867421 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.2594593549 | Sep 01 03:33:12 AM UTC 24 | Sep 01 03:33:14 AM UTC 24 | 4624237 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.52970434 | Sep 01 03:33:12 AM UTC 24 | Sep 01 03:33:14 AM UTC 24 | 5123067 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.3187711769 | Sep 01 03:33:12 AM UTC 24 | Sep 01 03:33:14 AM UTC 24 | 5142836 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3513301211 | Sep 01 03:33:13 AM UTC 24 | Sep 01 03:33:15 AM UTC 24 | 4877654 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.882484632 | Sep 01 03:33:14 AM UTC 24 | Sep 01 03:33:16 AM UTC 24 | 5164493 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.1483382951 | Sep 01 03:33:14 AM UTC 24 | Sep 01 03:33:16 AM UTC 24 | 5085446 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.1091114104 | Sep 01 03:33:14 AM UTC 24 | Sep 01 03:33:16 AM UTC 24 | 5054685 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.3883253382 | Sep 01 03:33:15 AM UTC 24 | Sep 01 03:33:17 AM UTC 24 | 5288078 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2819385222 | Sep 01 03:33:16 AM UTC 24 | Sep 01 03:33:17 AM UTC 24 | 5084207 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1513993352 | Sep 01 03:33:17 AM UTC 24 | Sep 01 03:33:18 AM UTC 24 | 4879464 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1028083814 | Sep 01 03:33:17 AM UTC 24 | Sep 01 03:33:18 AM UTC 24 | 4602550 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.249778664 | Sep 01 03:33:17 AM UTC 24 | Sep 01 03:33:18 AM UTC 24 | 5145834 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3840242130 | Sep 01 03:33:17 AM UTC 24 | Sep 01 03:33:18 AM UTC 24 | 4947855 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3771539475 | Sep 01 03:33:18 AM UTC 24 | Sep 01 03:33:19 AM UTC 24 | 5414219 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.3586743211 | Sep 01 03:33:18 AM UTC 24 | Sep 01 03:33:20 AM UTC 24 | 4453817 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2411734087 | Sep 01 03:33:19 AM UTC 24 | Sep 01 03:33:21 AM UTC 24 | 4413620 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.3263249214 | Sep 01 03:33:19 AM UTC 24 | Sep 01 03:33:21 AM UTC 24 | 4627276 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.691035065 | Sep 01 03:33:19 AM UTC 24 | Sep 01 03:33:21 AM UTC 24 | 4707921 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3385605493 | Sep 01 03:33:19 AM UTC 24 | Sep 01 03:33:21 AM UTC 24 | 4700961 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.3187711769 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5142836 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 03:33:12 AM UTC 24 |
| Finished | Sep 01 03:33:14 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187711769 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.prim_esc_test.3187711769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3840242130 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4947855 ps |
| CPU time | 0.63 seconds |
| Started | Sep 01 03:33:17 AM UTC 24 |
| Finished | Sep 01 03:33:18 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840242130 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.prim_esc_test.3840242130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.52970434 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5123067 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 03:33:12 AM UTC 24 |
| Finished | Sep 01 03:33:14 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52970434 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.52970434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.3586743211 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4453817 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 03:33:18 AM UTC 24 |
| Finished | Sep 01 03:33:20 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586743211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.prim_esc_test.3586743211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.2411734087 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4413620 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 03:33:19 AM UTC 24 |
| Finished | Sep 01 03:33:21 AM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411734087 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.prim_esc_test.2411734087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.2708648343 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4867421 ps |
| CPU time | 0.83 seconds |
| Started | Sep 01 03:33:09 AM UTC 24 |
| Finished | Sep 01 03:33:11 AM UTC 24 |
| Peak memory | 156152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708648343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.2708648343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1513993352 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4879464 ps |
| CPU time | 0.6 seconds |
| Started | Sep 01 03:33:17 AM UTC 24 |
| Finished | Sep 01 03:33:18 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513993352 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.prim_esc_test.1513993352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1028083814 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4602550 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 03:33:17 AM UTC 24 |
| Finished | Sep 01 03:33:18 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028083814 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.prim_esc_test.1028083814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.249778664 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5145834 ps |
| CPU time | 0.6 seconds |
| Started | Sep 01 03:33:17 AM UTC 24 |
| Finished | Sep 01 03:33:18 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249778664 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 12.prim_esc_test.249778664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3771539475 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5414219 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 03:33:18 AM UTC 24 |
| Finished | Sep 01 03:33:19 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771539475 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.prim_esc_test.3771539475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.3263249214 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4627276 ps |
| CPU time | 0.6 seconds |
| Started | Sep 01 03:33:19 AM UTC 24 |
| Finished | Sep 01 03:33:21 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263249214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.prim_esc_test.3263249214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3385605493 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4700961 ps |
| CPU time | 0.64 seconds |
| Started | Sep 01 03:33:19 AM UTC 24 |
| Finished | Sep 01 03:33:21 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385605493 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.3385605493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.691035065 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4707921 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 03:33:19 AM UTC 24 |
| Finished | Sep 01 03:33:21 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691035065 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 19.prim_esc_test.691035065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.2594593549 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4624237 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 03:33:12 AM UTC 24 |
| Finished | Sep 01 03:33:14 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594593549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.prim_esc_test.2594593549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3513301211 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4877654 ps |
| CPU time | 0.65 seconds |
| Started | Sep 01 03:33:13 AM UTC 24 |
| Finished | Sep 01 03:33:15 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513301211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.prim_esc_test.3513301211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.1483382951 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5085446 ps |
| CPU time | 0.6 seconds |
| Started | Sep 01 03:33:14 AM UTC 24 |
| Finished | Sep 01 03:33:16 AM UTC 24 |
| Peak memory | 156000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483382951 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.prim_esc_test.1483382951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.1091114104 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5054685 ps |
| CPU time | 0.62 seconds |
| Started | Sep 01 03:33:14 AM UTC 24 |
| Finished | Sep 01 03:33:16 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091114104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.prim_esc_test.1091114104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.882484632 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5164493 ps |
| CPU time | 0.46 seconds |
| Started | Sep 01 03:33:14 AM UTC 24 |
| Finished | Sep 01 03:33:16 AM UTC 24 |
| Peak memory | 157328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882484632 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 7.prim_esc_test.882484632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.3883253382 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5288078 ps |
| CPU time | 0.61 seconds |
| Started | Sep 01 03:33:15 AM UTC 24 |
| Finished | Sep 01 03:33:17 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3883253382 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.prim_esc_test.3883253382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2819385222 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5084207 ps |
| CPU time | 0.59 seconds |
| Started | Sep 01 03:33:16 AM UTC 24 |
| Finished | Sep 01 03:33:17 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819385222 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.prim_esc_test.2819385222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_31/prim_esc-sim-vcs/9.prim_esc_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |