| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.74 | 87.74 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 78.57 | 78.57 | 82.22 | 82.22 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.3420893149 |
| 90.05 | 2.31 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 10.71 | 84.44 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.4178856645 |
| 91.17 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3633190365 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.736786177 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1902352686 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2282464646 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1929576939 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.3826767571 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3454989796 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.1780711447 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1053745805 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.3808303327 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.1696718630 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.4111294315 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3140965236 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.3409796134 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.1710850211 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.458371104 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.4249954636 |
| /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.91705232 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.3409796134 | Sep 03 09:00:25 PM UTC 24 | Sep 03 09:00:26 PM UTC 24 | 5214681 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3633190365 | Sep 03 09:00:25 PM UTC 24 | Sep 03 09:00:26 PM UTC 24 | 4661986 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.736786177 | Sep 03 09:00:25 PM UTC 24 | Sep 03 09:00:26 PM UTC 24 | 5247704 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1902352686 | Sep 03 09:00:25 PM UTC 24 | Sep 03 09:00:26 PM UTC 24 | 5465566 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.1710850211 | Sep 03 09:00:25 PM UTC 24 | Sep 03 09:00:26 PM UTC 24 | 5125540 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.4178856645 | Sep 03 09:00:25 PM UTC 24 | Sep 03 09:00:27 PM UTC 24 | 4945198 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.3420893149 | Sep 03 09:00:26 PM UTC 24 | Sep 03 09:00:27 PM UTC 24 | 4380944 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.458371104 | Sep 03 09:00:26 PM UTC 24 | Sep 03 09:00:27 PM UTC 24 | 4710502 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.4249954636 | Sep 03 09:00:26 PM UTC 24 | Sep 03 09:00:27 PM UTC 24 | 4193922 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2282464646 | Sep 03 09:00:26 PM UTC 24 | Sep 03 09:00:27 PM UTC 24 | 4867750 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1929576939 | Sep 03 09:00:26 PM UTC 24 | Sep 03 09:00:27 PM UTC 24 | 4444613 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.91705232 | Sep 03 09:00:26 PM UTC 24 | Sep 03 09:00:27 PM UTC 24 | 4666848 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1053745805 | Sep 03 09:00:26 PM UTC 24 | Sep 03 09:00:28 PM UTC 24 | 4689201 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.1780711447 | Sep 03 09:00:26 PM UTC 24 | Sep 03 09:00:28 PM UTC 24 | 4937280 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.3826767571 | Sep 03 09:00:26 PM UTC 24 | Sep 03 09:00:28 PM UTC 24 | 5215764 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3454989796 | Sep 03 09:00:26 PM UTC 24 | Sep 03 09:00:28 PM UTC 24 | 4958300 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.3808303327 | Sep 03 09:00:26 PM UTC 24 | Sep 03 09:00:28 PM UTC 24 | 5369710 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.1696718630 | Sep 03 09:00:26 PM UTC 24 | Sep 03 09:00:28 PM UTC 24 | 5111541 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.4111294315 | Sep 03 09:00:27 PM UTC 24 | Sep 03 09:00:29 PM UTC 24 | 4867330 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3140965236 | Sep 03 09:00:27 PM UTC 24 | Sep 03 09:00:29 PM UTC 24 | 5398656 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.3420893149 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4380944 ps |
| CPU time | 0.35 seconds |
| Started | Sep 03 09:00:26 PM UTC 24 |
| Finished | Sep 03 09:00:27 PM UTC 24 |
| Peak memory | 157004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420893149 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.prim_esc_test.3420893149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.4178856645 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4945198 ps |
| CPU time | 0.35 seconds |
| Started | Sep 03 09:00:25 PM UTC 24 |
| Finished | Sep 03 09:00:27 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178856645 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.prim_esc_test.4178856645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3633190365 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4661986 ps |
| CPU time | 0.34 seconds |
| Started | Sep 03 09:00:25 PM UTC 24 |
| Finished | Sep 03 09:00:26 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633190365 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.3633190365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.736786177 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5247704 ps |
| CPU time | 0.33 seconds |
| Started | Sep 03 09:00:25 PM UTC 24 |
| Finished | Sep 03 09:00:26 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736786177 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 3.prim_esc_test.736786177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1902352686 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5465566 ps |
| CPU time | 0.36 seconds |
| Started | Sep 03 09:00:25 PM UTC 24 |
| Finished | Sep 03 09:00:26 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902352686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.prim_esc_test.1902352686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.2282464646 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4867750 ps |
| CPU time | 0.39 seconds |
| Started | Sep 03 09:00:26 PM UTC 24 |
| Finished | Sep 03 09:00:27 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282464646 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.prim_esc_test.2282464646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1929576939 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4444613 ps |
| CPU time | 0.35 seconds |
| Started | Sep 03 09:00:26 PM UTC 24 |
| Finished | Sep 03 09:00:27 PM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929576939 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.prim_esc_test.1929576939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.3826767571 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 5215764 ps |
| CPU time | 0.36 seconds |
| Started | Sep 03 09:00:26 PM UTC 24 |
| Finished | Sep 03 09:00:28 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826767571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.prim_esc_test.3826767571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3454989796 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4958300 ps |
| CPU time | 0.36 seconds |
| Started | Sep 03 09:00:26 PM UTC 24 |
| Finished | Sep 03 09:00:28 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454989796 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.prim_esc_test.3454989796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.1780711447 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4937280 ps |
| CPU time | 0.35 seconds |
| Started | Sep 03 09:00:26 PM UTC 24 |
| Finished | Sep 03 09:00:28 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780711447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.prim_esc_test.1780711447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1053745805 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4689201 ps |
| CPU time | 0.32 seconds |
| Started | Sep 03 09:00:26 PM UTC 24 |
| Finished | Sep 03 09:00:28 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053745805 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.prim_esc_test.1053745805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.3808303327 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5369710 ps |
| CPU time | 0.39 seconds |
| Started | Sep 03 09:00:26 PM UTC 24 |
| Finished | Sep 03 09:00:28 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808303327 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.prim_esc_test.3808303327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.1696718630 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5111541 ps |
| CPU time | 0.33 seconds |
| Started | Sep 03 09:00:26 PM UTC 24 |
| Finished | Sep 03 09:00:28 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696718630 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.prim_esc_test.1696718630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.4111294315 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4867330 ps |
| CPU time | 0.32 seconds |
| Started | Sep 03 09:00:27 PM UTC 24 |
| Finished | Sep 03 09:00:29 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111294315 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.4111294315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3140965236 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5398656 ps |
| CPU time | 0.4 seconds |
| Started | Sep 03 09:00:27 PM UTC 24 |
| Finished | Sep 03 09:00:29 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140965236 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.prim_esc_test.3140965236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.3409796134 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5214681 ps |
| CPU time | 0.33 seconds |
| Started | Sep 03 09:00:25 PM UTC 24 |
| Finished | Sep 03 09:00:26 PM UTC 24 |
| Peak memory | 156152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409796134 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.prim_esc_test.3409796134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.1710850211 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5125540 ps |
| CPU time | 0.34 seconds |
| Started | Sep 03 09:00:25 PM UTC 24 |
| Finished | Sep 03 09:00:26 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710850211 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.prim_esc_test.1710850211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.458371104 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4710502 ps |
| CPU time | 0.35 seconds |
| Started | Sep 03 09:00:26 PM UTC 24 |
| Finished | Sep 03 09:00:27 PM UTC 24 |
| Peak memory | 156776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458371104 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 7.prim_esc_test.458371104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.4249954636 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4193922 ps |
| CPU time | 0.33 seconds |
| Started | Sep 03 09:00:26 PM UTC 24 |
| Finished | Sep 03 09:00:27 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249954636 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.prim_esc_test.4249954636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.91705232 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4666848 ps |
| CPU time | 0.35 seconds |
| Started | Sep 03 09:00:26 PM UTC 24 |
| Finished | Sep 03 09:00:27 PM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91705232 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.91705232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/prim_esc-sim-vcs/9.prim_esc_test/latest |
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