| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.17 | 94.50 | 87.80 | 100.00 | 92.86 | 86.67 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.06 | 86.06 | 90.83 | 90.83 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 80.00 | 80.00 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.2603360486 |
| 88.18 | 2.12 | 91.74 | 0.92 | 87.80 | 2.44 | 100.00 | 0.00 | 82.14 | 7.14 | 82.22 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.730183953 |
| 89.45 | 1.27 | 93.58 | 1.83 | 87.80 | 0.00 | 100.00 | 0.00 | 85.71 | 3.57 | 84.44 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.4106082080 |
| 90.57 | 1.12 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 3.57 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.530478690 |
| 91.17 | 0.60 | 94.50 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.67 | 0.00 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.3907898123 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3193163850 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1364755480 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1050353981 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.731850638 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1737501115 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.3795952945 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3171555323 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.551201343 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.66355156 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2766307056 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.10360066 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2274636451 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.3898618515 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.2364817501 |
| /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2564975515 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3193163850 | Sep 09 03:09:12 AM UTC 24 | Sep 09 03:09:13 AM UTC 24 | 4789568 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1364755480 | Sep 09 03:09:12 AM UTC 24 | Sep 09 03:09:13 AM UTC 24 | 5325806 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.2603360486 | Sep 09 03:09:12 AM UTC 24 | Sep 09 03:09:13 AM UTC 24 | 4943813 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.66355156 | Sep 09 03:09:12 AM UTC 24 | Sep 09 03:09:13 AM UTC 24 | 5407550 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2766307056 | Sep 09 03:09:12 AM UTC 24 | Sep 09 03:09:14 AM UTC 24 | 5189172 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2274636451 | Sep 09 03:09:12 AM UTC 24 | Sep 09 03:09:14 AM UTC 24 | 5355374 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.10360066 | Sep 09 03:09:12 AM UTC 24 | Sep 09 03:09:14 AM UTC 24 | 4615066 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.2364817501 | Sep 09 03:09:12 AM UTC 24 | Sep 09 03:09:14 AM UTC 24 | 5096364 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.3898618515 | Sep 09 03:09:12 AM UTC 24 | Sep 09 03:09:14 AM UTC 24 | 5165255 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.530478690 | Sep 09 03:09:13 AM UTC 24 | Sep 09 03:09:15 AM UTC 24 | 4949390 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.731850638 | Sep 09 03:09:13 AM UTC 24 | Sep 09 03:09:15 AM UTC 24 | 5557502 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1050353981 | Sep 09 03:09:13 AM UTC 24 | Sep 09 03:09:15 AM UTC 24 | 5152634 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2564975515 | Sep 09 03:09:13 AM UTC 24 | Sep 09 03:09:15 AM UTC 24 | 4879551 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.730183953 | Sep 09 03:09:13 AM UTC 24 | Sep 09 03:09:15 AM UTC 24 | 4904030 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.3907898123 | Sep 09 03:09:15 AM UTC 24 | Sep 09 03:09:16 AM UTC 24 | 4598104 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.4106082080 | Sep 09 03:09:15 AM UTC 24 | Sep 09 03:09:16 AM UTC 24 | 4895352 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1737501115 | Sep 09 03:09:15 AM UTC 24 | Sep 09 03:09:16 AM UTC 24 | 4663899 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.3795952945 | Sep 09 03:09:15 AM UTC 24 | Sep 09 03:09:16 AM UTC 24 | 4511575 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3171555323 | Sep 09 03:09:15 AM UTC 24 | Sep 09 03:09:16 AM UTC 24 | 4226289 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.551201343 | Sep 09 03:09:15 AM UTC 24 | Sep 09 03:09:16 AM UTC 24 | 4796128 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.2603360486 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4943813 ps |
| CPU time | 0.32 seconds |
| Started | Sep 09 03:09:12 AM UTC 24 |
| Finished | Sep 09 03:09:13 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603360486 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.prim_esc_test.2603360486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.730183953 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4904030 ps |
| CPU time | 0.35 seconds |
| Started | Sep 09 03:09:13 AM UTC 24 |
| Finished | Sep 09 03:09:15 AM UTC 24 |
| Peak memory | 156064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730183953 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 12.prim_esc_test.730183953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.4106082080 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4895352 ps |
| CPU time | 0.32 seconds |
| Started | Sep 09 03:09:15 AM UTC 24 |
| Finished | Sep 09 03:09:16 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106082080 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.prim_esc_test.4106082080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.530478690 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4949390 ps |
| CPU time | 0.32 seconds |
| Started | Sep 09 03:09:13 AM UTC 24 |
| Finished | Sep 09 03:09:15 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530478690 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 10.prim_esc_test.530478690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.3907898123 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4598104 ps |
| CPU time | 0.32 seconds |
| Started | Sep 09 03:09:15 AM UTC 24 |
| Finished | Sep 09 03:09:16 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907898123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.prim_esc_test.3907898123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3193163850 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4789568 ps |
| CPU time | 0.31 seconds |
| Started | Sep 09 03:09:12 AM UTC 24 |
| Finished | Sep 09 03:09:13 AM UTC 24 |
| Peak memory | 156152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193163850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.3193163850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.1364755480 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 5325806 ps |
| CPU time | 0.31 seconds |
| Started | Sep 09 03:09:12 AM UTC 24 |
| Finished | Sep 09 03:09:13 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364755480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.prim_esc_test.1364755480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.1050353981 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5152634 ps |
| CPU time | 0.32 seconds |
| Started | Sep 09 03:09:13 AM UTC 24 |
| Finished | Sep 09 03:09:15 AM UTC 24 |
| Peak memory | 155748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050353981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 11.prim_esc_test.1050353981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.731850638 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5557502 ps |
| CPU time | 0.31 seconds |
| Started | Sep 09 03:09:13 AM UTC 24 |
| Finished | Sep 09 03:09:15 AM UTC 24 |
| Peak memory | 156060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731850638 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 13.prim_esc_test.731850638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1737501115 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4663899 ps |
| CPU time | 0.33 seconds |
| Started | Sep 09 03:09:15 AM UTC 24 |
| Finished | Sep 09 03:09:16 AM UTC 24 |
| Peak memory | 156084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737501115 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.prim_esc_test.1737501115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.3795952945 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4511575 ps |
| CPU time | 0.33 seconds |
| Started | Sep 09 03:09:15 AM UTC 24 |
| Finished | Sep 09 03:09:16 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795952945 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.prim_esc_test.3795952945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.3171555323 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4226289 ps |
| CPU time | 0.32 seconds |
| Started | Sep 09 03:09:15 AM UTC 24 |
| Finished | Sep 09 03:09:16 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171555323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.3171555323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.551201343 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4796128 ps |
| CPU time | 0.35 seconds |
| Started | Sep 09 03:09:15 AM UTC 24 |
| Finished | Sep 09 03:09:16 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551201343 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 19.prim_esc_test.551201343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.66355156 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 5407550 ps |
| CPU time | 0.32 seconds |
| Started | Sep 09 03:09:12 AM UTC 24 |
| Finished | Sep 09 03:09:13 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66355156 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.66355156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.2766307056 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5189172 ps |
| CPU time | 0.31 seconds |
| Started | Sep 09 03:09:12 AM UTC 24 |
| Finished | Sep 09 03:09:14 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766307056 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.prim_esc_test.2766307056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.10360066 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4615066 ps |
| CPU time | 0.33 seconds |
| Started | Sep 09 03:09:12 AM UTC 24 |
| Finished | Sep 09 03:09:14 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10360066 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.10360066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2274636451 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5355374 ps |
| CPU time | 0.32 seconds |
| Started | Sep 09 03:09:12 AM UTC 24 |
| Finished | Sep 09 03:09:14 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274636451 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.prim_esc_test.2274636451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.3898618515 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5165255 ps |
| CPU time | 0.35 seconds |
| Started | Sep 09 03:09:12 AM UTC 24 |
| Finished | Sep 09 03:09:14 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898618515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.prim_esc_test.3898618515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.2364817501 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5096364 ps |
| CPU time | 0.31 seconds |
| Started | Sep 09 03:09:12 AM UTC 24 |
| Finished | Sep 09 03:09:14 AM UTC 24 |
| Peak memory | 156088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364817501 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.prim_esc_test.2364817501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2564975515 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4879551 ps |
| CPU time | 0.35 seconds |
| Started | Sep 09 03:09:13 AM UTC 24 |
| Finished | Sep 09 03:09:15 AM UTC 24 |
| Peak memory | 155672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564975515 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.prim_esc_test.2564975515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/prim_esc-sim-vcs/9.prim_esc_test/latest |
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