| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 91.17 | 94.50 | 87.80 | 100.00 | 92.86 | 86.67 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 87.15 | 87.15 | 92.66 | 92.66 | 87.80 | 87.80 | 100.00 | 100.00 | 75.00 | 75.00 | 82.22 | 82.22 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.3323937893 |
| 88.86 | 1.71 | 93.58 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 82.14 | 7.14 | 84.44 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.2961216689 |
| 90.57 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 89.29 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.610889184 |
| 91.17 | 0.60 | 94.50 | 0.00 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 3.57 | 86.67 | 0.00 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3928206182 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.1349284154 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.2831933871 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1575077169 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.630699694 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.2887515578 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3098201223 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1529530616 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.2182581729 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.65467893 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2846688644 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3093504886 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.356412790 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.3679642166 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2617283750 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.660361584 |
| /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3139648692 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.1349284154 | Sep 10 10:36:09 PM UTC 24 | Sep 10 10:36:11 PM UTC 24 | 4838329 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.2831933871 | Sep 10 10:36:09 PM UTC 24 | Sep 10 10:36:11 PM UTC 24 | 4788191 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.356412790 | Sep 10 10:36:09 PM UTC 24 | Sep 10 10:36:11 PM UTC 24 | 5244464 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.3323937893 | Sep 10 10:36:09 PM UTC 24 | Sep 10 10:36:11 PM UTC 24 | 5069975 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3928206182 | Sep 10 10:36:09 PM UTC 24 | Sep 10 10:36:11 PM UTC 24 | 5159012 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2617283750 | Sep 10 10:36:11 PM UTC 24 | Sep 10 10:36:12 PM UTC 24 | 4553867 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.3679642166 | Sep 10 10:36:11 PM UTC 24 | Sep 10 10:36:12 PM UTC 24 | 5426030 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.660361584 | Sep 10 10:36:11 PM UTC 24 | Sep 10 10:36:12 PM UTC 24 | 4794705 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.610889184 | Sep 10 10:36:11 PM UTC 24 | Sep 10 10:36:12 PM UTC 24 | 5217066 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3139648692 | Sep 10 10:36:11 PM UTC 24 | Sep 10 10:36:12 PM UTC 24 | 4498396 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.630699694 | Sep 10 10:36:11 PM UTC 24 | Sep 10 10:36:12 PM UTC 24 | 5099470 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1575077169 | Sep 10 10:36:11 PM UTC 24 | Sep 10 10:36:13 PM UTC 24 | 4450533 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.2961216689 | Sep 10 10:36:11 PM UTC 24 | Sep 10 10:36:13 PM UTC 24 | 4875005 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.2887515578 | Sep 10 10:36:11 PM UTC 24 | Sep 10 10:36:13 PM UTC 24 | 4386369 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3098201223 | Sep 10 10:36:12 PM UTC 24 | Sep 10 10:36:14 PM UTC 24 | 4861060 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1529530616 | Sep 10 10:36:12 PM UTC 24 | Sep 10 10:36:14 PM UTC 24 | 4416592 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.65467893 | Sep 10 10:36:12 PM UTC 24 | Sep 10 10:36:14 PM UTC 24 | 4522029 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.2182581729 | Sep 10 10:36:12 PM UTC 24 | Sep 10 10:36:14 PM UTC 24 | 5102186 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2846688644 | Sep 10 10:36:12 PM UTC 24 | Sep 10 10:36:14 PM UTC 24 | 4893356 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3093504886 | Sep 10 10:36:12 PM UTC 24 | Sep 10 10:36:14 PM UTC 24 | 4854373 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.3323937893 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5069975 ps |
| CPU time | 0.59 seconds |
| Started | Sep 10 10:36:09 PM UTC 24 |
| Finished | Sep 10 10:36:11 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323937893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.prim_esc_test.3323937893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.2961216689 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4875005 ps |
| CPU time | 0.58 seconds |
| Started | Sep 10 10:36:11 PM UTC 24 |
| Finished | Sep 10 10:36:13 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961216689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.prim_esc_test.2961216689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.610889184 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5217066 ps |
| CPU time | 0.58 seconds |
| Started | Sep 10 10:36:11 PM UTC 24 |
| Finished | Sep 10 10:36:12 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610889184 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 7.prim_esc_test.610889184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3928206182 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5159012 ps |
| CPU time | 0.58 seconds |
| Started | Sep 10 10:36:09 PM UTC 24 |
| Finished | Sep 10 10:36:11 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928206182 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.prim_esc_test.3928206182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.1349284154 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4838329 ps |
| CPU time | 0.62 seconds |
| Started | Sep 10 10:36:09 PM UTC 24 |
| Finished | Sep 10 10:36:11 PM UTC 24 |
| Peak memory | 156144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349284154 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.1349284154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.2831933871 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4788191 ps |
| CPU time | 0.6 seconds |
| Started | Sep 10 10:36:09 PM UTC 24 |
| Finished | Sep 10 10:36:11 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831933871 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.prim_esc_test.2831933871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.1575077169 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4450533 ps |
| CPU time | 0.6 seconds |
| Started | Sep 10 10:36:11 PM UTC 24 |
| Finished | Sep 10 10:36:13 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575077169 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.prim_esc_test.1575077169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.630699694 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5099470 ps |
| CPU time | 0.59 seconds |
| Started | Sep 10 10:36:11 PM UTC 24 |
| Finished | Sep 10 10:36:12 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630699694 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 11.prim_esc_test.630699694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.2887515578 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4386369 ps |
| CPU time | 0.61 seconds |
| Started | Sep 10 10:36:11 PM UTC 24 |
| Finished | Sep 10 10:36:13 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887515578 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.prim_esc_test.2887515578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.3098201223 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4861060 ps |
| CPU time | 0.59 seconds |
| Started | Sep 10 10:36:12 PM UTC 24 |
| Finished | Sep 10 10:36:14 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098201223 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.prim_esc_test.3098201223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.1529530616 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4416592 ps |
| CPU time | 0.58 seconds |
| Started | Sep 10 10:36:12 PM UTC 24 |
| Finished | Sep 10 10:36:14 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529530616 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.prim_esc_test.1529530616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.2182581729 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 5102186 ps |
| CPU time | 0.58 seconds |
| Started | Sep 10 10:36:12 PM UTC 24 |
| Finished | Sep 10 10:36:14 PM UTC 24 |
| Peak memory | 155092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182581729 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.prim_esc_test.2182581729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.65467893 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4522029 ps |
| CPU time | 0.48 seconds |
| Started | Sep 10 10:36:12 PM UTC 24 |
| Finished | Sep 10 10:36:14 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65467893 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.65467893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2846688644 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4893356 ps |
| CPU time | 0.5 seconds |
| Started | Sep 10 10:36:12 PM UTC 24 |
| Finished | Sep 10 10:36:14 PM UTC 24 |
| Peak memory | 154976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846688644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.2846688644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3093504886 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4854373 ps |
| CPU time | 0.6 seconds |
| Started | Sep 10 10:36:12 PM UTC 24 |
| Finished | Sep 10 10:36:14 PM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093504886 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.prim_esc_test.3093504886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.356412790 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5244464 ps |
| CPU time | 0.57 seconds |
| Started | Sep 10 10:36:09 PM UTC 24 |
| Finished | Sep 10 10:36:11 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356412790 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.prim_esc_test.356412790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.3679642166 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 5426030 ps |
| CPU time | 0.61 seconds |
| Started | Sep 10 10:36:11 PM UTC 24 |
| Finished | Sep 10 10:36:12 PM UTC 24 |
| Peak memory | 156072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679642166 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.prim_esc_test.3679642166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.2617283750 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4553867 ps |
| CPU time | 0.56 seconds |
| Started | Sep 10 10:36:11 PM UTC 24 |
| Finished | Sep 10 10:36:12 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617283750 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.prim_esc_test.2617283750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.660361584 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4794705 ps |
| CPU time | 0.56 seconds |
| Started | Sep 10 10:36:11 PM UTC 24 |
| Finished | Sep 10 10:36:12 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660361584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 8.prim_esc_test.660361584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.3139648692 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4498396 ps |
| CPU time | 0.57 seconds |
| Started | Sep 10 10:36:11 PM UTC 24 |
| Finished | Sep 10 10:36:12 PM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139648692 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.prim_esc_test.3139648692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/prim_esc-sim-vcs/9.prim_esc_test/latest |
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