| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 92.29 | 95.41 | 87.80 | 100.00 | 96.43 | 88.89 | 85.19 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 86.06 | 86.06 | 90.83 | 90.83 | 85.37 | 85.37 | 100.00 | 100.00 | 75.00 | 75.00 | 80.00 | 80.00 | 85.19 | 85.19 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2112812860 |
| 89.45 | 3.39 | 93.58 | 2.75 | 87.80 | 2.44 | 100.00 | 0.00 | 85.71 | 10.71 | 84.44 | 4.44 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3339117145 |
| 91.17 | 1.71 | 94.50 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 92.86 | 7.14 | 86.67 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3038427986 |
| 92.29 | 1.12 | 95.41 | 0.92 | 87.80 | 0.00 | 100.00 | 0.00 | 96.43 | 3.57 | 88.89 | 2.22 | 85.19 | 0.00 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.4044073358 |
| Name |
|---|
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.3181056614 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.70895186 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.341574937 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3234093307 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.1620276254 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.4236213411 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.1079196144 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.1679149783 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2135082244 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.259870584 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.3988822316 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3823754452 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.287294932 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.1951510631 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.1366360348 |
| /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2326913271 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3339117145 | Sep 18 03:36:01 AM UTC 24 | Sep 18 03:36:02 AM UTC 24 | 5039503 ps | ||
| T2 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.4044073358 | Sep 18 03:36:01 AM UTC 24 | Sep 18 03:36:02 AM UTC 24 | 4801940 ps | ||
| T3 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.259870584 | Sep 18 03:36:01 AM UTC 24 | Sep 18 03:36:02 AM UTC 24 | 4886027 ps | ||
| T4 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3823754452 | Sep 18 03:36:02 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 4714662 ps | ||
| T10 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2112812860 | Sep 18 03:36:02 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 4628189 ps | ||
| T13 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.3988822316 | Sep 18 03:36:02 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 5371758 ps | ||
| T11 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.1366360348 | Sep 18 03:36:02 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 5477307 ps | ||
| T14 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.1951510631 | Sep 18 03:36:02 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 5046032 ps | ||
| T15 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.287294932 | Sep 18 03:36:02 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 4583944 ps | ||
| T12 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.3181056614 | Sep 18 03:36:02 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 5209362 ps | ||
| T8 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2326913271 | Sep 18 03:36:02 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 4967257 ps | ||
| T16 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.70895186 | Sep 18 03:36:02 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 4789039 ps | ||
| T5 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.341574937 | Sep 18 03:36:02 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 4630936 ps | ||
| T6 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3234093307 | Sep 18 03:36:02 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 4441939 ps | ||
| T7 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.1620276254 | Sep 18 03:36:03 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 5325941 ps | ||
| T17 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3038427986 | Sep 18 03:36:03 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 4715746 ps | ||
| T18 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.4236213411 | Sep 18 03:36:03 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 4385068 ps | ||
| T9 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.1679149783 | Sep 18 03:36:03 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 4819824 ps | ||
| T19 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.1079196144 | Sep 18 03:36:03 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 5311096 ps | ||
| T20 | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2135082244 | Sep 18 03:36:03 AM UTC 24 | Sep 18 03:36:04 AM UTC 24 | 4601748 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/5.prim_esc_test.2112812860 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 4628189 ps |
| CPU time | 0.36 seconds |
| Started | Sep 18 03:36:02 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112812860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 5.prim_esc_test.2112812860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/5.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/0.prim_esc_test.3339117145 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 5039503 ps |
| CPU time | 0.35 seconds |
| Started | Sep 18 03:36:01 AM UTC 24 |
| Finished | Sep 18 03:36:02 AM UTC 24 |
| Peak memory | 156140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339117145 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.prim_esc_test.3339117145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/0.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/19.prim_esc_test.3038427986 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4715746 ps |
| CPU time | 0.33 seconds |
| Started | Sep 18 03:36:03 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038427986 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 19.prim_esc_test.3038427986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/19.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/1.prim_esc_test.4044073358 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 4801940 ps |
| CPU time | 0.35 seconds |
| Started | Sep 18 03:36:01 AM UTC 24 |
| Finished | Sep 18 03:36:02 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044073358 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.prim_esc_test.4044073358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/1.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/10.prim_esc_test.3181056614 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5209362 ps |
| CPU time | 0.33 seconds |
| Started | Sep 18 03:36:02 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 155984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181056614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 10.prim_esc_test.3181056614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/10.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/11.prim_esc_test.70895186 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 4789039 ps |
| CPU time | 0.33 seconds |
| Started | Sep 18 03:36:02 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70895186 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.70895186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/11.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/12.prim_esc_test.341574937 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4630936 ps |
| CPU time | 0.32 seconds |
| Started | Sep 18 03:36:02 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341574937 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 12.prim_esc_test.341574937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/12.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/13.prim_esc_test.3234093307 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4441939 ps |
| CPU time | 0.37 seconds |
| Started | Sep 18 03:36:02 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234093307 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 13.prim_esc_test.3234093307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/13.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/14.prim_esc_test.1620276254 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 5325941 ps |
| CPU time | 0.35 seconds |
| Started | Sep 18 03:36:03 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620276254 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 14.prim_esc_test.1620276254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/14.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/15.prim_esc_test.4236213411 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 4385068 ps |
| CPU time | 0.33 seconds |
| Started | Sep 18 03:36:03 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236213411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 15.prim_esc_test.4236213411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/15.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/16.prim_esc_test.1079196144 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 5311096 ps |
| CPU time | 0.34 seconds |
| Started | Sep 18 03:36:03 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079196144 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 16.prim_esc_test.1079196144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/16.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/17.prim_esc_test.1679149783 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4819824 ps |
| CPU time | 0.33 seconds |
| Started | Sep 18 03:36:03 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679149783 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.prim_esc_test.1679149783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/17.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/18.prim_esc_test.2135082244 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4601748 ps |
| CPU time | 0.34 seconds |
| Started | Sep 18 03:36:03 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135082244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 18.prim_esc_test.2135082244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/18.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/2.prim_esc_test.259870584 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4886027 ps |
| CPU time | 0.33 seconds |
| Started | Sep 18 03:36:01 AM UTC 24 |
| Finished | Sep 18 03:36:02 AM UTC 24 |
| Peak memory | 156080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259870584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.prim_esc_test.259870584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/2.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/3.prim_esc_test.3988822316 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 5371758 ps |
| CPU time | 0.38 seconds |
| Started | Sep 18 03:36:02 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988822316 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 3.prim_esc_test.3988822316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/3.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/4.prim_esc_test.3823754452 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 4714662 ps |
| CPU time | 0.34 seconds |
| Started | Sep 18 03:36:02 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823754452 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 4.prim_esc_test.3823754452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/4.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/6.prim_esc_test.287294932 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4583944 ps |
| CPU time | 0.36 seconds |
| Started | Sep 18 03:36:02 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 155960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287294932 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nul l -cm_name 6.prim_esc_test.287294932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/6.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/7.prim_esc_test.1951510631 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 5046032 ps |
| CPU time | 0.35 seconds |
| Started | Sep 18 03:36:02 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951510631 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 7.prim_esc_test.1951510631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/7.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/8.prim_esc_test.1366360348 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5477307 ps |
| CPU time | 0.33 seconds |
| Started | Sep 18 03:36:02 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366360348 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 8.prim_esc_test.1366360348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/8.prim_esc_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default/9.prim_esc_test.2326913271 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4967257 ps |
| CPU time | 0.37 seconds |
| Started | Sep 18 03:36:02 AM UTC 24 |
| Finished | Sep 18 03:36:04 AM UTC 24 |
| Peak memory | 156076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326913271 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/nu ll -cm_name 9.prim_esc_test.2326913271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_17/prim_esc-sim-vcs/9.prim_esc_test/latest |
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